[M] Change in coreboot[main]: soc/amd: add functions to retrieve I3C controller info

[Felix Held (Code Review)]

Attention is currently required from: Martin L Roth.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87280?usp=email )

Change subject: soc/amd: add functions to retrieve I3C controller info
......................................................................

soc/amd: add functions to retrieve I3C controller info

Similarly to how things are done for the I2C controller configuration,
implement the 'soc_get_i3c_ctrlr_info' function in all SoCs that have
I3C controllers. This function returns the contents of the SoC's
'i3c_ctrlr' array containing the base addresses and ACPI names of the
I3C controllers. This function will eventually be called by the common
I3C code which will be implemented in future patches.

Change-Id: Ib23fd896925770f49e567324bc8d12ac4c0944bd
Signed-off-by: Felix Held 
---
M src/soc/amd/common/block/include/amdblocks/i2c.h
M src/soc/amd/genoa_poc/i2c.c
M src/soc/amd/genoa_poc/include/soc/iomap.h
M src/soc/amd/glinda/i2c.c
M src/soc/amd/glinda/include/soc/iomap.h
M src/soc/amd/mendocino/i2c.c
M src/soc/amd/mendocino/include/soc/iomap.h
M src/soc/amd/phoenix/i2c.c
M src/soc/amd/phoenix/include/soc/iomap.h
9 files changed, 64 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/87280/1

diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h
index b02487a..94ac173 100644
--- a/src/soc/amd/common/block/include/amdblocks/i2c.h
+++ b/src/soc/amd/common/block/include/amdblocks/i2c.h
@@ -68,6 +68,11 @@
    enum i2c_pad_rx_level rx_level;
 };

+struct soc_i3c_ctrlr_info {
+	uintptr_t bar;
+	const char *acpi_name;
+};
+
 void fch_i2c_pad_init(unsigned int bus,
    	      enum i2c_speed speed,
    	      const struct i2c_pad_control *ctrl);
@@ -94,4 +99,7 @@
 /* Reset I2C peripherals. */
 void sb_reset_i2c_peripherals(const struct soc_i2c_peripheral_reset_info *reset_info);

+/* Getter function to get the SoC I3C controller information. */
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs);
+
 #endif /* AMD_COMMON_BLOCK_I2C_H */
diff --git a/src/soc/amd/genoa_poc/i2c.c b/src/soc/amd/genoa_poc/i2c.c
index 6436e3d..3d18123 100644
--- a/src/soc/amd/genoa_poc/i2c.c
+++ b/src/soc/amd/genoa_poc/i2c.c
@@ -25,6 +25,13 @@
    { I2C_MASTER_MODE, APU_I2C5_BASE, "I2C5" }
 };

+static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
+	{ APU_I3C0_BASE, "I3C0" },
+	{ APU_I3C1_BASE, "I3C1" },
+	{ APU_I3C2_BASE, "I3C2" },
+	{ APU_I3C3_BASE, "I3C3" }
+};
+
 void reset_i2c_peripherals(void)
 {
    const struct soc_amd_genoa_poc_config *cfg = config_of_soc();
@@ -54,3 +61,9 @@
    *num_buses = ARRAY_SIZE(config->i2c);
    return config->i2c;
 }
+
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(i3c_ctrlr);
+	return i3c_ctrlr;
+}
diff --git a/src/soc/amd/genoa_poc/include/soc/iomap.h b/src/soc/amd/genoa_poc/include/soc/iomap.h
index f7a1bac..179fb3d 100644
--- a/src/soc/amd/genoa_poc/include/soc/iomap.h
+++ b/src/soc/amd/genoa_poc/include/soc/iomap.h
@@ -6,6 +6,7 @@
 #define I2C_MASTER_DEV_COUNT		6
 #define I2C_PERIPHERAL_DEV_COUNT	0
 #define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
+#define I3C_CTRLR_COUNT			4

#define SPI_BASE_ADDRESS		0xfec10000

diff --git a/src/soc/amd/glinda/i2c.c b/src/soc/amd/glinda/i2c.c
index ab45ff5..99184ac 100644
--- a/src/soc/amd/glinda/i2c.c
+++ b/src/soc/amd/glinda/i2c.c
@@ -43,6 +43,13 @@
 }
 #endif

+static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
+	{ APU_I3C0_BASE, "I3C0" },
+	{ APU_I3C1_BASE, "I3C1" },
+	{ APU_I3C2_BASE, "I3C2" },
+	{ APU_I3C3_BASE, "I3C3" }
+};
+
 void reset_i2c_peripherals(void)
 {
    const struct soc_amd_glinda_config *cfg = config_of_soc();
@@ -77,3 +84,9 @@
    *num_buses = ARRAY_SIZE(config->i2c);
    return config->i2c;
 }
+
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(i3c_ctrlr);
+	return i3c_ctrlr;
+}
diff --git a/src/soc/amd/glinda/include/soc/iomap.h b/src/soc/amd/glinda/include/soc/iomap.h
index bb68e17..32890dd 100644
--- a/src/soc/amd/glinda/include/soc/iomap.h
+++ b/src/soc/amd/glinda/include/soc/iomap.h
@@ -6,6 +6,7 @@
 #define I2C_MASTER_DEV_COUNT		4
 #define I2C_PERIPHERAL_DEV_COUNT	0 /* TODO: Only master for now. */
 #define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
+#define I3C_CTRLR_COUNT			4

#if ENV_X86

diff --git a/src/soc/amd/mendocino/i2c.c b/src/soc/amd/mendocino/i2c.c
index 92433a7..51c34f6 100644
--- a/src/soc/amd/mendocino/i2c.c
+++ b/src/soc/amd/mendocino/i2c.c
@@ -41,6 +41,13 @@
 }
 #endif

+static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
+	{ APU_I3C0_BASE, "I3C0" },
+	{ APU_I3C1_BASE, "I3C1" },
+	{ APU_I3C2_BASE, "I3C2" },
+	{ APU_I3C3_BASE, "I3C3" }
+};
+
 void reset_i2c_peripherals(void)
 {
    const struct soc_amd_mendocino_config *cfg = config_of_soc();
@@ -75,3 +82,9 @@
    *num_buses = ARRAY_SIZE(config->i2c);
    return config->i2c;
 }
+
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(i3c_ctrlr);
+	return i3c_ctrlr;
+}
diff --git a/src/soc/amd/mendocino/include/soc/iomap.h b/src/soc/amd/mendocino/include/soc/iomap.h
index bffdb5f..81a5d17 100644
--- a/src/soc/amd/mendocino/include/soc/iomap.h
+++ b/src/soc/amd/mendocino/include/soc/iomap.h
@@ -6,6 +6,7 @@
 #define I2C_MASTER_DEV_COUNT		4
 #define I2C_PERIPHERAL_DEV_COUNT	0 /* TODO: Only master for now. */
 #define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
+#define I3C_CTRLR_COUNT			4

#if ENV_X86

diff --git a/src/soc/amd/phoenix/i2c.c b/src/soc/amd/phoenix/i2c.c
index e069c23..cfcf9a8 100644
--- a/src/soc/amd/phoenix/i2c.c
+++ b/src/soc/amd/phoenix/i2c.c
@@ -41,6 +41,13 @@
 }
 #endif

+static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
+	{ APU_I3C0_BASE, "I3C0" },
+	{ APU_I3C1_BASE, "I3C1" },
+	{ APU_I3C2_BASE, "I3C2" },
+	{ APU_I3C3_BASE, "I3C3" }
+};
+
 void reset_i2c_peripherals(void)
 {
    const struct soc_amd_phoenix_config *cfg = config_of_soc();
@@ -75,3 +82,9 @@
    *num_buses = ARRAY_SIZE(config->i2c);
    return config->i2c;
 }
+
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(i3c_ctrlr);
+	return i3c_ctrlr;
+}
diff --git a/src/soc/amd/phoenix/include/soc/iomap.h b/src/soc/amd/phoenix/include/soc/iomap.h
index 63d8b08..d5dadaf 100644
--- a/src/soc/amd/phoenix/include/soc/iomap.h
+++ b/src/soc/amd/phoenix/include/soc/iomap.h
@@ -6,6 +6,7 @@
 #define I2C_MASTER_DEV_COUNT		4
 #define I2C_PERIPHERAL_DEV_COUNT	0 /* TODO: Only master for now. */
 #define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
+#define I3C_CTRLR_COUNT			4

#if ENV_X86