Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46420 )
Change subject: mb/intel/adlrvp: Enable Hybrid storage mode ......................................................................
mb/intel/adlrvp: Enable Hybrid storage mode
TEST=Build and test booting ADL RVP form NVMe and Optane localhost ~ # lspci -d :f1a6 Show all the NVMe devices and be really verbose localhost ~ # lspci -vvvd :f1a6 Print PCIe lane capabilities and configurations for all the NVMe devices.
Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46420/1
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index fadf602..c5103ce 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -72,6 +72,9 @@ # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below register "PcieClkSrcUsage[6]" = "0xff"
+ # Hybrid storage mode + register "HybridStorageMode" = "1" + register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46420 )
Change subject: mb/intel/adlrvp: Enable Hybrid storage mode ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/46420/1/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46420/1/src/mainboard/intel/adlrvp/... PS1, Line 76: register "HybridStorageMode" = "1" nit: Maybe put it next to the PCIe RP settings for Optane?
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46420
to look at the new patch set (#2).
Change subject: mb/intel/adlrvp: Enable Hybrid storage mode ......................................................................
mb/intel/adlrvp: Enable Hybrid storage mode
TEST=Build and test booting ADL RVP form NVMe and Optane localhost ~ # lspci -d :f1a6 Show all the NVMe devices and be really verbose localhost ~ # lspci -vvvd :f1a6 Print PCIe lane capabilities and configurations for all the NVMe devices.
Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46420/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46420 )
Change subject: mb/intel/adlrvp: Enable Hybrid storage mode ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46420/1/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46420/1/src/mainboard/intel/adlrvp/... PS1, Line 76: register "HybridStorageMode" = "1"
nit: Maybe put it next to the PCIe RP settings for Optane?
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46420 )
Change subject: mb/intel/adlrvp: Enable Hybrid storage mode ......................................................................
Patch Set 2: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46420 )
Change subject: mb/intel/adlrvp: Enable Hybrid storage mode ......................................................................
mb/intel/adlrvp: Enable Hybrid storage mode
TEST=Build and test booting ADL RVP form NVMe and Optane localhost ~ # lspci -d :f1a6 Show all the NVMe devices and be really verbose localhost ~ # lspci -vvvd :f1a6 Print PCIe lane capabilities and configurations for all the NVMe devices.
Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46420 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index fadf602..818f32f 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -61,6 +61,8 @@
# Enable PCH PCIE RP 11 for optane register "PcieRpEnable[10]" = "1" + # Hybrid storage mode + register "HybridStorageMode" = "1"
# Enable CPU PCIE RP 1 using PEG CLK 0 register "PcieClkSrcUsage[0]" = "0x40"
-
Angel Pons (Code Review) -
Subrata Banik (Code Review)