Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Modified memory dimm settings

[Kin Wai Ng (Code Review)]

Hello Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi,

I'd like you to do a code review. Please visit

https://review.coreboot.org/25229

to review the following change.

Change subject: mainboard/intel/coffeelake_rvp: Modified memory dimm settings
......................................................................

mainboard/intel/coffeelake_rvp: Modified memory dimm settings

1. Hardcoded SPD Addresses
2. Modified memory dimm values to suit CFL-H RVP11

Change-Id: I4011de101d9a35e4735fc8491015aa56ebe80e7e
Signed-off-by: Ng Kin Wai 
---
M src/mainboard/intel/coffeelake_rvp/romstage.c
M src/mainboard/intel/coffeelake_rvp/spd/spd_util.c
2 files changed, 16 insertions(+), 21 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/25229/1

diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c
old mode 100644
new mode 100755
index e0699da..a2c719b
--- a/src/mainboard/intel/coffeelake_rvp/romstage.c
+++ b/src/mainboard/intel/coffeelake_rvp/romstage.c
@@ -36,8 +36,8 @@
    mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
    mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);

-	mem_cfg->DqPinsInterleaved = 0;
-	mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */
+	mem_cfg->DqPinsInterleaved = 1;
+	mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA/CHB */
    mem_cfg->ECT = 1; /* Early Command Training Enabled */
    spd_index = 2;

@@ -51,4 +51,9 @@
    mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
    mem_cfg->RefClk = 0; /* Auto Select CLK freq */
    mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+
+	mem_cfg->SpdAddressTable[0] = 0xA0;
+	mem_cfg->SpdAddressTable[1] = 0xA2;
+	mem_cfg->SpdAddressTable[2] = 0xA4;
+	mem_cfg->SpdAddressTable[3] = 0xA6;
 }
diff --git a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c
old mode 100644
new mode 100755
index 4e2f31f..ece6b6c
--- a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c
+++ b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c
@@ -23,8 +23,8 @@
 {
    /* DQ byte map Ch0 */
    const u8 dq_map[12] = {
-		0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 ,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+		0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+		0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 };

memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
 }
@@ -32,8 +32,8 @@
 void mainboard_fill_dq_map_ch1(void *dq_map_ptr)
 {
    const u8 dq_map[12] = {
-		0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+		0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+		0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 };

memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
 }
@@ -41,27 +41,17 @@
 void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)
 {
    /* DQS CPU<>DRAM map Ch0 */
-	const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 };
+	const u8 dqs_map_h[8] = { 0, 1, 3, 2, 4, 5, 6, 7 };

-	const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };
-
-	if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))
-		memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
-	else
-		memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
+	memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h));
 }

void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)
 {
    /* DQS CPU<>DRAM map Ch1 */
-	const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 };
+	const u8 dqs_map_h[8] = { 1, 0, 4, 5, 2, 3, 6, 7 };

-	const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };
-
-	if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))
-		memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
-	else
-		memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
+	memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h));
 }

void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
@@ -75,7 +65,7 @@
 {
    /* Rcomp target */
    static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
-			80, 40, 40, 40, 30 };
+			100, 33, 32, 33, 28 };

memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
 }