Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45789 )
Change subject: soc/intel: Make use of IA common LPC code block ......................................................................
soc/intel: Make use of IA common LPC code block
This patch removes redundant LPC functions from SoC directory and refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/cpx/chip.c 9 files changed, 20 insertions(+), 645 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45789/1
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 50af9ee..c7f7a29 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -90,115 +90,13 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { const config_t *config = dev->chip_info;
/* Legacy initialization */ isa_dma_init(); - pch_misc_init(); + lpc_pch_misc_init();
/* Enable CLKRUN_EN for power gating LPC */ lpc_enable_pci_clk_cntl(); @@ -207,8 +105,8 @@ lpc_set_serirq_mode(config->serirq_mode);
/* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + lpc_pch_enable_ioapic(); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 538a81e..4de54e3 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -282,7 +282,7 @@ lpc_set_gen_decode_range(gen_io_dec); soc_setup_dmi_pcr_io_dec(gen_io_dec); if (ENV_PAYLOAD_LOADER) - soc_pch_pirq_init(dev); + lpc_pch_pirq_init(); }
void lpc_enable_pci_clk_cntl(void) diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index 7133997..92782a08 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -64,113 +64,11 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_enable_ioapic(const struct device *dev) -{ - uint32_t reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - uint8_t int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(NMI_STS_CNT) & 0xf0); - outb((reg8 | (1 << 2)), NMI_STS_CNT); - - /* Disable NMI sources */ - outb((1 << 7), NMI_EN); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ isa_dma_init(); - pch_misc_init(); + lpc_pch_misc_init();
/* Enable CLKRUN_EN for power gating ESPI */ lpc_enable_pci_clk_cntl(); @@ -182,8 +80,8 @@ lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + lpc_pch_enable_ioapic(); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 1497c8d..71cbbe3 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -83,113 +83,11 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ isa_dma_init(); - pch_misc_init(); + lpc_pch_misc_init();
/* Enable CLKRUN_EN for power gating ESPI */ lpc_enable_pci_clk_cntl(); @@ -201,8 +99,8 @@ lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + lpc_pch_enable_ioapic(); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index bf82067..2061a29 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -65,113 +65,11 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ isa_dma_init(); - pch_misc_init(); + lpc_pch_misc_init();
/* Enable CLKRUN_EN for power gating ESPI */ lpc_enable_pci_clk_cntl(); @@ -183,8 +81,8 @@ lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + lpc_pch_enable_ioapic(); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 62050c9..ad75f02 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -215,71 +215,3 @@ /* TCO Irq enable/disable */ params->TcoIrqEnable = config->TcoIrqEnable; } - -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - struct device *irq_dev; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 7dc90f0..ecea3e2 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -29,29 +29,6 @@ return skl_lpc_fixed_mmio_ranges; }
-static void pch_enable_ioapic(struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} - void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) { const config_t *config = config_of(dev); @@ -72,10 +49,6 @@ }
static const struct reg_script pch_misc_init_script[] = { - /* Setup NMI on errors, disable SERR */ - REG_IO_RMW8(0x61, ~0xf0, (1 << 2)), - /* Disable NMI sources */ - REG_IO_OR8(0x70, (1 << 7)), /* Enable BIOS updates outside of SMM */ REG_PCI_RMW8(0xdc, ~(1 << 5), 0), REG_SCRIPT_END @@ -87,6 +60,7 @@
/* Legacy initialization */ isa_dma_init(); + lpc_pch_misc_init(); reg_script_run_on_dev(PCH_DEV_LPC, pch_misc_init_script);
/* Enable CLKRUN_EN for power gating LPC */ @@ -96,8 +70,8 @@ lpc_set_serirq_mode(config->serirq_mode);
/* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + lpc_pch_enable_ioapic(); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); } diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 513da5a..2ae8679 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -71,113 +71,11 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ isa_dma_init(); - pch_misc_init(); + lpc_pch_misc_init();
/* Enable CLKRUN_EN for power gating ESPI */ lpc_enable_pci_clk_cntl(); @@ -189,8 +87,8 @@ lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + lpc_pch_enable_ioapic(); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 2c445f9..2fcc192 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -545,27 +545,6 @@ DEV_FUNC_EXIT(dev); }
-static void pch_enable_ioapic(const struct device *dev) -{ - uint32_t reg32; - - set_ioapic_id((void *)IO_APIC_ADDR, 2); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 1); - - reg32 &= ~0x00ff0000; - reg32 |= (C620_IOAPIC_REDIR_ENTRIES - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 1, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 3, 1); -} - struct pci_operations soc_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -592,7 +571,7 @@ { printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(false); - pch_enable_ioapic(NULL); + lpc_pch_enable_ioapic(); setup_lapic(); p2sb_unhide(); }
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45789
to look at the new patch set (#4).
Change subject: soc/intel: Make use of IA common LPC code block ......................................................................
soc/intel: Make use of IA common LPC code block
This patch removes redundant LPC functions from SoC directory and refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/cpx/chip.c 9 files changed, 20 insertions(+), 645 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45789/4
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45789
to look at the new patch set (#5).
Change subject: soc/intel: Make use of IA common LPC code block ......................................................................
soc/intel: Make use of IA common LPC code block
This patch removes redundant LPC functions from SoC directory and refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/cpx/chip.c 9 files changed, 20 insertions(+), 645 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45789/5
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45789
to look at the new patch set (#6).
Change subject: soc/intel: Make use of common LPC code block ......................................................................
soc/intel: Make use of common LPC code block
This patch removes redundant LPC functions from SoC directory and refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/cpx/chip.c 9 files changed, 20 insertions(+), 645 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45789/6
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45789
to look at the new patch set (#7).
Change subject: soc/intel: Make use of common LPC code block ......................................................................
soc/intel: Make use of common LPC code block
This patch removes redundant LPC functions from SoC directory and refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/cpx/chip.c 9 files changed, 21 insertions(+), 645 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45789/7
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45789 )
Change subject: soc/intel: Make use of common LPC code block ......................................................................
Patch Set 7: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/45789/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45789/7//COMMIT_MSG@10 PS7, Line 10: refer from block/lpc directory. This patch is a bit large... What I would do is combine CB:45787 and this, then split it into one patch per function:
soc/intel: Move `pch_enable_ioapic` to common code soc/intel: Move `pch_pirq_init` to common code soc/intel: Move `pch_misc_init` to common code
This would result in slightly smaller patches. Also, it would be easier to review, as the common code would be in the same patch as the per-SoC removals. What do you think?
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45789
to look at the new patch set (#8).
Change subject: soc/intel: Move pch_misc_init() to common code ......................................................................
soc/intel: Move pch_misc_init() to common code
List of changes: 1. Rename pch_misc_init() as lpc_pch_misc_init() and move into common block code. 2. Removes redundant LPC functions from SoC directory and refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c 8 files changed, 25 insertions(+), 69 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45789/8
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45789 )
Change subject: soc/intel: Move pch_misc_init() to common code ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45789/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45789/7//COMMIT_MSG@10 PS7, Line 10: refer from block/lpc directory.
This patch is a bit large... What I would do is combine CB:45787 and this, then split it into one patch per function:
soc/intel: Move `pch_enable_ioapic` to common code
https://review.coreboot.org/c/coreboot/+/45787/7
soc/intel: Move `pch_pirq_init` to common code
https://review.coreboot.org/c/coreboot/+/45809/1
soc/intel: Move `pch_misc_init` to common code
https://review.coreboot.org/c/coreboot/+/45789
This would result in slightly smaller patches. Also, it would be easier to review, as the common code would be in the same patch as the per-SoC removals. What do you think?
yes, already done. thanks
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45789 )
Change subject: soc/intel: Move pch_misc_init() to common code ......................................................................
Patch Set 8: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/45789/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45789/8//COMMIT_MSG@12 PS8, Line 12: Removes nit: Remove
https://review.coreboot.org/c/coreboot/+/45789/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45789/8/src/soc/intel/common/block/... PS8, Line 396: 0x61 For another patch: Use macros for these registers
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45789
to look at the new patch set (#9).
Change subject: soc/intel: Move pch_misc_init() to common code ......................................................................
soc/intel: Move pch_misc_init() to common code
List of changes: 1. Rename pch_misc_init() as lpc_pch_misc_init() and move into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c 8 files changed, 25 insertions(+), 69 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45789/9
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45789 )
Change subject: soc/intel: Move pch_misc_init() to common code ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45789/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45789/8//COMMIT_MSG@12 PS8, Line 12: Removes
nit: Remove
Ack
https://review.coreboot.org/c/coreboot/+/45789/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45789/8/src/soc/intel/common/block/... PS8, Line 396: 0x61
For another patch: Use macros for these registers
sure, will make it clean in another patch
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45789
to look at the new patch set (#10).
Change subject: soc/intel: Move pch_misc_init() to common code ......................................................................
soc/intel: Move pch_misc_init() to common code
List of changes: 1. Move pch_misc_init() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. 3. Create macros for IO port 0x61 and 0x70 as applicable.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c 8 files changed, 25 insertions(+), 64 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45789/10
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45789
to look at the new patch set (#11).
Change subject: soc/intel: Move pch_misc_init() to common code ......................................................................
soc/intel: Move pch_misc_init() to common code
List of changes: 1. Move pch_misc_init() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. 3. Create macros for IO port 0x61 and 0x70 as applicable.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/elkhartlake/include/soc/espi.h M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c 9 files changed, 25 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45789/11
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45789 )
Change subject: soc/intel: Move pch_misc_init() to common code ......................................................................
Patch Set 11: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/45789/11/src/soc/intel/common/block... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45789/11/src/soc/intel/common/block... PS11, Line 15: : : #define PPI_PORT_B 0x61 : #define SERR_DIS (1 << 2) : #define CMOS_NMI 0x70 : #define NMI_DIS (1 << 7) nit: move these next to the function using them. Otherwise, one needs to scroll up hundreds of lines to see what they mean.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45789
to look at the new patch set (#12).
Change subject: soc/intel: Move pch_misc_init() to common code ......................................................................
soc/intel: Move pch_misc_init() to common code
List of changes: 1. Move pch_misc_init() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. 3. Create macros for IO port 0x61 and 0x70 as applicable.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/elkhartlake/include/soc/espi.h M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c 9 files changed, 25 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45789/12
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45789 )
Change subject: soc/intel: Move pch_misc_init() to common code ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45789/11/src/soc/intel/common/block... File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/45789/11/src/soc/intel/common/block... PS11, Line 15: : : #define PPI_PORT_B 0x61 : #define SERR_DIS (1 << 2) : #define CMOS_NMI 0x70 : #define NMI_DIS (1 << 7)
nit: move these next to the function using them. […]
Ack
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45789 )
Change subject: soc/intel: Move pch_misc_init() to common code ......................................................................
Patch Set 12: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45789 )
Change subject: soc/intel: Move pch_misc_init() to common code ......................................................................
Patch Set 12: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45789 )
Change subject: soc/intel: Move pch_misc_init() to common code ......................................................................
soc/intel: Move pch_misc_init() to common code
List of changes: 1. Move pch_misc_init() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. 3. Create macros for IO port 0x61 and 0x70 as applicable.
TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45789 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/elkhartlake/include/soc/espi.h M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c 9 files changed, 25 insertions(+), 66 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index e220678..b21c117 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -90,18 +90,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { const config_t *config = dev->chip_info; diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 52b0ff8..b04df76 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -109,5 +109,11 @@ void pch_enable_ioapic(void); /* Retrieve and setup PCH LPC interrupt routing. */ void pch_pirq_init(void); +/* + * LPC MISC programming + * 1. Setup NMI on errors, disable SERR + * 2. Disable NMI sources + */ +void pch_misc_init(void);
#endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index d189a5e..67dd661 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -386,3 +386,21 @@ pci_write_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_LINE, int_line); } } + +#define PPI_PORT_B 0x61 +#define SERR_DIS (1 << 2) +#define CMOS_NMI 0x70 +#define NMI_DIS (1 << 7) + +/* LPC MISC programming */ +void pch_misc_init(void) +{ + uint8_t reg8; + + /* Setup NMI on errors, disable SERR */ + reg8 = (inb(PPI_PORT_B)) & 0xf0; + outb((reg8 | SERR_DIS), PPI_PORT_B); + + /* Disable NMI sources */ + outb(NMI_DIS, CMOS_NMI); +} diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index 6e6f887..a531fcc 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -64,18 +64,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(NMI_STS_CNT) & 0xf0); - outb((reg8 | (1 << 2)), NMI_STS_CNT); - - /* Disable NMI sources */ - outb((1 << 7), NMI_EN); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ diff --git a/src/soc/intel/elkhartlake/include/soc/espi.h b/src/soc/intel/elkhartlake/include/soc/espi.h index 6c26158..65ee732 100644 --- a/src/soc/intel/elkhartlake/include/soc/espi.h +++ b/src/soc/intel/elkhartlake/include/soc/espi.h @@ -22,8 +22,6 @@ #define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ #define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ #define LGMR 0x98 /* ESPI Generic Memory Range */ -#define NMI_EN 0x70 -#define NMI_STS_CNT 0x61 #define PCCTL 0xE0 /* PCI Clock Control */ #define CLKRUN_EN (1 << 0)
diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 388d9fa..7f9ff2f 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -83,18 +83,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index ef1ed95..0977857 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -65,18 +65,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 0eaeb9f..f9c6639 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -49,10 +49,6 @@ }
static const struct reg_script pch_misc_init_script[] = { - /* Setup NMI on errors, disable SERR */ - REG_IO_RMW8(0x61, ~0xf0, (1 << 2)), - /* Disable NMI sources */ - REG_IO_OR8(0x70, (1 << 7)), /* Enable BIOS updates outside of SMM */ REG_PCI_RMW8(0xdc, ~(1 << 5), 0), REG_SCRIPT_END @@ -64,6 +60,7 @@
/* Legacy initialization */ isa_dma_init(); + pch_misc_init(); reg_script_run_on_dev(PCH_DEV_LPC, pch_misc_init_script);
/* Enable CLKRUN_EN for power gating LPC */ diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 668e95f..acd3b12 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -71,18 +71,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); }
-static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */
-
Angel Pons (Code Review) -
Subrata Banik (Code Review)
-
Tim Wawrzynczak (Code Review)