Martin Roth has uploaded this change for review. ( https://review.coreboot.org/26777
Change subject: mainboard/google/kahlee: Remove Kahlee variant ......................................................................
mainboard/google/kahlee: Remove Kahlee variant
This code is no longer needed. Removing Kahlee options allows some Kconfig options to be optimized.
BUG=b:77693343 TEST=Build Grunt, verify that nothing's changed.
Change-Id: I4eeeee7f35381bba8760c8a530251c475d0ee29b Signed-off-by: Martin Roth martinroth@google.com --- M src/mainboard/google/kahlee/BiosCallOuts.c M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kahlee/Kconfig.name M src/mainboard/google/kahlee/mainboard.c D src/mainboard/google/kahlee/variants/kahlee/Makefile.inc D src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c D src/mainboard/google/kahlee/variants/kahlee/chromeos.fmd D src/mainboard/google/kahlee/variants/kahlee/devicetree.cb D src/mainboard/google/kahlee/variants/kahlee/gpio.c D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/audio.asl D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/gpe.asl D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/mainboard.asl D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/routing.asl D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/sleep.asl D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/thermal.asl D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/touchpad.asl D src/mainboard/google/kahlee/variants/kahlee/include/variant/ec.h D src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h D src/mainboard/google/kahlee/variants/kahlee/include/variant/thermal.h D src/mainboard/google/kahlee/variants/kahlee/memory.c 20 files changed, 9 insertions(+), 778 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/26777/1
diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c index 2ed1843..7f7e575 100644 --- a/src/mainboard/google/kahlee/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/BiosCallOuts.c @@ -15,13 +15,7 @@
#include <amdblocks/agesawrapper.h> #include <amdblocks/BiosCallOuts.h> -#include <soc/southbridge.h> -#include <stdlib.h> -#include <baseboard/variants.h>
void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) { - /* SDHCI/MMC configuration */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE)) - FchParams_env->Sd.SdSlotType = 1; // EMMC } diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index b44e3bd..03d5265 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -18,8 +18,7 @@ select SOC_AMD_STONEYRIDGE_FT4 select ALWAYS_LOAD_OPROM select ALWAYS_RUN_OPROM - select BOARD_ROMSIZE_KB_8192 if BOARD_GOOGLE_KAHLEE - select BOARD_ROMSIZE_KB_16384 if !BOARD_GOOGLE_KAHLEE + select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC select DRIVERS_PS2_KEYBOARD select EC_GOOGLE_CHROMEEC @@ -30,13 +29,18 @@ select GFXUMA select GOOGLE_SMBIOS_MAINBOARD_VERSION select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM if BOARD_GOOGLE_KAHLEE select SERIRQ_CONTINUOUS_MODE select STONEYRIDGE_UART select SOC_AMD_PSP_SELECTABLE_SMU_FW select SOC_AMD_SMU_FANLESS select HAVE_ACPI_RESUME - select DRIVERS_GENERIC_BH720 if !BOARD_GOOGLE_KAHLEE + select DRIVERS_GENERIC_BH720 + select I2C_TPM + select MAINBOARD_HAS_I2C_TPM_CR50 + select TPM2 + select DRIVERS_GENERIC_ADAU7002 + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219
if BOARD_GOOGLE_BASEBOARD_KAHLEE
@@ -48,13 +52,11 @@ string default "careena" if BOARD_GOOGLE_CAREENA default "grunt" if BOARD_GOOGLE_GRUNT - default "kahlee" if BOARD_GOOGLE_KAHLEE
config MAINBOARD_PART_NUMBER string default "Careena" if BOARD_GOOGLE_CAREENA default "Grunt" if BOARD_GOOGLE_GRUNT - default "Kahlee" if BOARD_GOOGLE_KAHLEE
config DEVICETREE string @@ -66,7 +68,6 @@
config FMDFILE string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/variants/$(CONFIG_VARIANT_DIR)/chromeos.fmd" if CHROMEOS && BOARD_GOOGLE_KAHLEE default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/variants/baseboard/chromeos.fmd" if CHROMEOS default "" help @@ -102,35 +103,17 @@ depends on CHROMEOS default "CAREENA TEST 8777" if BOARD_GOOGLE_CAREENA default "GRUNT TEST 8296" if BOARD_GOOGLE_GRUNT - default "KAHLEE TEST 6421" if BOARD_GOOGLE_KAHLEE
config AMD_FWM_POSITION_INDEX int default 1
-# Select this option to enable use of cr50 I2C TPM on kahlee -config KAHLEE_USE_I2C_TPM - bool - default y if !BOARD_GOOGLE_KAHLEE - select I2C_TPM - select MAINBOARD_HAS_I2C_TPM_CR50 - select TPM2 - config DRIVER_TPM_I2C_BUS hex - depends on KAHLEE_USE_I2C_TPM default 0x01
config DRIVER_TPM_I2C_ADDR hex - depends on KAHLEE_USE_I2C_TPM default 0x50
-config GRUNT_AUDIO - bool - default y if !BOARD_GOOGLE_KAHLEE - select DRIVERS_GENERIC_ADAU7002 - select DRIVERS_GENERIC_MAX98357A - select DRIVERS_I2C_DA7219 - endif # BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/Kconfig.name b/src/mainboard/google/kahlee/Kconfig.name index 98f9be1..4f58a01 100644 --- a/src/mainboard/google/kahlee/Kconfig.name +++ b/src/mainboard/google/kahlee/Kconfig.name @@ -6,6 +6,3 @@ config BOARD_GOOGLE_GRUNT bool "-> Grunt" select BOARD_GOOGLE_BASEBOARD_KAHLEE -config BOARD_GOOGLE_KAHLEE - bool "-> Kahlee" - select BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index e090401..c2c9be3 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -44,46 +44,6 @@ * MP Tables. TODO: Make ACPI use these values too. */
-// TODO: Move these to board variant specific file -#if IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE) -const u8 mainboard_picr_data[] = { - [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, - [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x03, - [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, - [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, - [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, - [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, - [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, -}; - -const u8 mainboard_intr_data[] = { - [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, - [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, - [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, - [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, - [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; -#else const u8 mainboard_picr_data[] = { [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x1F, 0x1F, 0x1F, [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, @@ -121,7 +81,6 @@ [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; -#endif
/* * This table defines the index into the picr/intr_data tables for each @@ -184,9 +143,7 @@ i2c_soc_init();
/* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */ - if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE)) - pm_write8(PM_PCIB_CFG, - pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE); + pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE); }
/************************************************* diff --git a/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc b/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc deleted file mode 100644 index ab91501..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc +++ /dev/null @@ -1,23 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2017 Google, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -bootblock-y += gpio.c -bootblock-y += OemCustomize.c - -romstage-y += OemCustomize.c -romstage-y += gpio.c -romstage-y += memory.c - -ramstage-y += gpio.c diff --git a/src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c deleted file mode 100644 index 568ed31..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <amdblocks/agesawrapper.h> -#include <variant/gpio.h> - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, - 2, 1, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmL0sL1, 0, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, - 2, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmL0sL1, PCIE_0_RST, 0) - }, - /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) for Card Reader */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, - 2, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmL0sL1, PCIE_1_RST, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for NC */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2), - PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, - 2, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmL0sL1, PCIE_2_RST, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3), - PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, - 2, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmL0sL1, PCIE_3_RST, 0) - }, -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* DDI0 - eDP */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1) - }, - /* DDI1 - DP */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) - }, - /* DDI2 - DP */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = (void *)PortList, - .DdiLinkList = (void *)DdiList -}; - -/*---------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This is the stub function will call the host environment through the - * binary block interface (call-out port) to provide a user hook opportunity. - * - * Parameters: - * @param[in] **PeiServices - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------*/ -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; - InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus; - InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth; -} diff --git a/src/mainboard/google/kahlee/variants/kahlee/chromeos.fmd b/src/mainboard/google/kahlee/variants/kahlee/chromeos.fmd deleted file mode 100644 index 4a4e3ca..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/chromeos.fmd +++ /dev/null @@ -1,40 +0,0 @@ -FLASH@0xFF800000 0x800000 { - SI_BIOS@0x0 0x800000 { - RW_SECTION_A@0x0 0x21E000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x20DFC0 - RW_FWID_A@0x21DFC0 0x40 - } - RW_SECTION_B@0x21E000 0x21E000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x20DFC0 - RW_FWID_B@0x21DFC0 0x40 - } - UNIFIED_MRC_CACHE@0x43C000 0x21000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - RW_VAR_MRC_CACHE@0x20000 0x1000 - } - RW_ELOG@0x45D000 0x4000 - - RW_SHARED@0x461000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x465000 0x2000 - RW_LEGACY@0x467000 0x100000 - RW_NVRAM@0x567000 0x5000 - RW_UNUSED@0x56C000 0x3000 - WP_RO@0x56F000 0x291000 { - RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x281000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x70000 - COREBOOT(CBFS)@0x71000 0x210000 - } - } - } -} diff --git a/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb deleted file mode 100644 index 22456b0..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip soc/amd/stoneyridge - - register "spd_addr_lookup" = " - { - { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 - }" - register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" - register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" - - device cpu_cluster 0 on - device lapic 10 on end - end - device domain 0 on - subsystemid 0x1022 0x1410 inherit - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # M.2 slot - device pci 2.3 on end # M.2 slot - device pci 2.4 on end # x1 PCIe slot - device pci 2.5 on end # Cardreader - # devices on the NB/SB Link, but on the same pci bus - device pci 8.0 on end # PSP - device pci 9.0 on end # PCIe Host Bridge - device pci 9.2 on end # HDA - device pci 10.0 on end # xHCI - device pci 11.0 on end # SATA - device pci 12.0 on end # EHCI - device pci 14.0 on # SM - chip drivers/generic/generic # dimm 0-0-0 - device i2c 50 on end - end - end # SM - device pci 14.3 on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC 0x790e - device pci 14.7 on end # SD - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - end #domain -end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c deleted file mode 100644 index 3072350..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/variants.h> -#include <soc/smi.h> -#include <soc/southbridge.h> -#include <stdlib.h> -#include <variant/gpio.h> - -/* - * As a rule of thumb, GPIO pins used by coreboot should be initialized at - * bootblock while GPIO pins used only by the OS should be initialized at - * ramstage. - */ -static const struct soc_amd_gpio gpio_set_stage_reset[] = { - /* AGPIO2, to become event generator */ - PAD_SCI(GPIO_2, PULL_UP, EDGE_LOW), - - /* SER_TX */ - PAD_NF(GPIO_8, SerPortTX_OUT, PULL_UP), - - /* SER RX */ - PAD_NF(GPIO_9, SerPortRX_OUT, PULL_UP), - - /* EC_IN_RW */ - PAD_GPI(GPIO_15, PULL_UP), - - /* APU_I2C_3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), - - /* APU_I2C_3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), - - /* AGPIO22 EC_SCI */ - PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), - - /* SPI_TPM_CS_L */ - PAD_NF(GPIO_76, SPI_TPM_CS_L, PULL_DOWN), - - /* BD_ID1 */ - PAD_GPI(GPIO_135, PULL_NONE), - - /* GPIO_136 - UART_FCH_RX_DEBUG_RX */ - PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), - - /* GPIO_138 - UART_FCH_TX_DEBUG_RX */ - PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), - - /* TPM_SERIRQ# */ - PAD_GPI(GPIO_139, PULL_UP), - - /* BD_ID2 */ - PAD_GPI(GPIO_140, PULL_NONE), - - /* APU_SPI_WP */ - PAD_GPI(GPIO_142, PULL_UP), - - /* BD_ID3 */ - PAD_GPI(GPIO_144, PULL_NONE), -}; - -static const struct soc_amd_gpio gpio_set_stage_ram[] = { - /* AGPIO 12 */ - PAD_GPI(GPIO_12, PULL_UP), - - /* TS_EN_SOC (TouchScreen enable GPIO) */ - PAD_GPO(GPIO_13, HIGH), - - /* CAM_PWRON (Camera enable GPIO) */ - PAD_GPO(GPIO_14, HIGH), - - /* APU_BT_ON# */ - PAD_GPO(GPIO_24, HIGH), - - /* DEVSLP1_SSD */ - PAD_NF(GPIO_67, DEVSLP0, PULL_UP), - - /* DEVSLP1_EMMC */ - /* No Connect for now. - * {GPIO_70, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT}, - */ - - /* CAM_LED# */ - PAD_GPO(GPIO_84, HIGH), - - /* TS_RST# (TouchScreen Reset) */ - PAD_GPO(GPIO_85, HIGH), - - /* WLAN_RST#_AUX */ - PAD_GPO(GPIO_119, HIGH), -}; - -const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(gpio_set_stage_reset); - return gpio_set_stage_reset; -} - -const struct soc_amd_gpio *variant_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(gpio_set_stage_ram); - return gpio_set_stage_ram; -} - -/* - * GPE setup table must match ACPI GPE ASL - * { gevent, gpe, direction, level } - */ -static const struct sci_source gpe_table[] = { - - /* EHCI USB_PME -> GPE24 */ - { - .scimap = 24, - .gpe = 24, - .direction = SMI_SCI_LVL_HIGH, - .level = SMI_SCI_LVL, - }, - - /* XHCIC0 -> GPE31 */ - { - .scimap = 56, - .gpe = 31, - .direction = SMI_SCI_LVL_HIGH, - .level = SMI_SCI_LVL, - }, -}; - -const struct sci_source *get_gpe_table(size_t *num) -{ - *num = ARRAY_SIZE(gpe_table); - return gpe_table; -} - -int variant_get_xhci_oc_map(uint16_t *map) -{ - *map = USB_OC2 << OC_PORT0_SHIFT; /* USB-A Port0/4 = OC2 */ - *map |= USB_OC0 << OC_PORT1_SHIFT; /* USB-C Port1/5 = OC0 */ - *map |= USB_OC1 << OC_PORT2_SHIFT; /* USB-C Port2/6 = OC1 */ - *map |= USB_OC_DISABLE << OC_PORT3_SHIFT; - return 0; -} - -int variant_get_ehci_oc_map(uint16_t *map) -{ - *map = USB_OC_DISABLE_ALL; - return 0; -} diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/audio.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/audio.asl deleted file mode 100644 index 031eafc..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/audio.asl +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Realtek Audio Codec */ -Device (RTEK) /* Audio Codec driver I2CS*/ -{ - Name (_ADR, 0) - Name (_HID, "10EC5650") - Name (_CID, "10EC5650") - Name (_DDN, "RTEK Codec Controller ") - Name (_UID, 1) - - Device (I2S) /* I2S machine driver for RT5650 */ - { - Name (_ADR, 1) - Name (_HID, "AMDI1002") - Name (_CID, "AMDI1002") - } - - Method (_CRS, 0x0, Serialized) - { - Name (SBUF, ResourceTemplate () - { - I2CSerialBus( - 0x1A, /* SlaveAddress: bus address */ - ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ - 400000, /* ConnectionSpeed: in Hz */ - AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ - "\_SB.I2CA", /* ResourceSource: I2C bus controller name */ - ) - - /* Jack Detect AGPIO90 */ - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\_SB.GPIO") { 90 } - }) - Return (SBUF) - } - - Method (_STA) - { - Return (0xF) - } -} diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/gpe.asl deleted file mode 100644 index 0a08774..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/gpe.asl +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/acpi/gpe.asl> diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/mainboard.asl deleted file mode 100644 index 159f935..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/mainboard.asl +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/acpi/mainboard.asl> -#include <variant/acpi/audio.asl> -#include <variant/acpi/touchpad.asl> diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/routing.asl deleted file mode 100644 index 233494f..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/routing.asl +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/acpi/routing.asl> diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/sleep.asl deleted file mode 100644 index c5a1557..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/sleep.asl +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/acpi/sleep.asl> diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/thermal.asl deleted file mode 100644 index 77137bb..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/thermal.asl +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/touchpad.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/touchpad.asl deleted file mode 100644 index 2babaf2..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/touchpad.asl +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (ETPA) -{ - Name (_HID, "ELAN0000") - Name (_DDN, "Elan Touchpad") - Name (_UID, 1) - Name (ISTP, 1) /* Touchpad */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x15, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\_SB.I2CD", /* ResourceSource */ - ) - GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,, - "\_SB.GPIO") { 0x5 } - }) - - /* Allow device to power off in S0 */ - Name (_S0W, 3) -} diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/ec.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/ec.h deleted file mode 100644 index 294a48d..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/ec.h +++ /dev/null @@ -1 +0,0 @@ -#include <baseboard/ec.h> diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h deleted file mode 100644 index 361e1eb..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __VARIANT_GPIO_H__ -#define __VARIANT_GPIO_H__ - -#ifndef __ACPI__ -#include <soc/gpio.h> - -/* - * Kahlee doesn't use MEM_CONFIG GPIOs, but they are required to build - * the baseboard weak memory_sku function. - */ -#define MEM_CONFIG0 0 -#define MEM_CONFIG1 0 -#define MEM_CONFIG2 0 -#define MEM_CONFIG3 0 - -/* CDX03 doesn't have a CR50 interrupt pin */ -#define H1_PCH_INT 0 - -/* SPI Write protect */ -#define CROS_WP_GPIO GPIO_142 -#define GPIO_EC_IN_RW GPIO_15 - -/* PCIe reset pins */ -#define PCIE_0_RST GPIO_119 -#define PCIE_1_RST 0 -#define PCIE_2_RST 0 -#define PCIE_3_RST 0 - -#endif /* _ACPI__ */ - -/* These define the GPE, not the GPIO. */ -#define EC_SCI_GPI 3 /* AGPIO 22 -> GPE 3 */ -#define EC_SMI_GPI 10 /* AGPIO 6 -> GPE 10 */ -#define EC_WAKE_GPI 8 /* AGPIO 2 -> GPE 8 */ - -#endif /* __VARIANT_GPIO_H__ */ diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/thermal.h deleted file mode 100644 index 2c983bb..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/thermal.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef THERMAL_H -#define THERMAL_H - -/* - * Stoney Ridge Thermal Requirements 12 (6W) - * TDP (W) 6 - * T die,max (°C) 95 - * T ctl,max 85 - * T die,lmt (default) 90 - * T ctl,lmt (default) 80 - */ - -/* Control TDP Settings */ -#define CTL_TDP_SENSOR_ID 0 /* EC TIN0 */ - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 94 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 85 - -#endif diff --git a/src/mainboard/google/kahlee/variants/kahlee/memory.c b/src/mainboard/google/kahlee/variants/kahlee/memory.c deleted file mode 100644 index 1c7c8a1..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/memory.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/variants.h> - -int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len) -{ - /* Return error so the default I2C SPD read is used */ - return -1; -}
-
Martin Roth (Code Review)