Change in coreboot[master]: mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51028 )

Change subject: mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP
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mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP

ADL-M LP4 RVP has command mirror enabled and we need to fill correct
value of this UPD to pass the MRC.
Also, Value of TxDqDqsRetraining is set to 1 by default and we need to
disable it for only ADL-M LP5 RVP.

BUG=None
BRANCH=None
TEST=UPD values has been pass correctly and MRC passes on LP4/LP5 board

Change-Id: I3e16b9a3d3e6a92dacba9d38782df408596ed5e1
Signed-off-by: Maulik V Vaghela 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51028
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/intel/adlrvp/memory.c
1 file changed, 12 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index 204744f..29eb744 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -20,6 +20,8 @@

.UserBd = BOARD_TYPE_MOBILE,

+	.LpDdrDqDqsReTraining = 1,
+
    .ddr_config = {
    	.dq_pins_interleaved = false,
    },
@@ -76,6 +78,8 @@
    	.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
    },

+	.LpDdrDqDqsReTraining = 1,
+
    .ect = true, /* Early Command Training */

.UserBd = BOARD_TYPE_MOBILE,
@@ -134,6 +138,8 @@

.ect = false, /* Early Command Training */

+	.LpDdrDqDqsReTraining = 1,
+
    .UserBd = BOARD_TYPE_MOBILE,

.lp5x_config = {
@@ -156,6 +162,8 @@

.UserBd = BOARD_TYPE_MOBILE,

+	.LpDdrDqDqsReTraining = 1,
+
    .ddr_config = {
    	.dq_pins_interleaved = false,
    }
@@ -214,6 +222,10 @@

.ect = true, /* Early Command Training */

+	.CmdMirror = 0xCC,
+
+	.LpDdrDqDqsReTraining = 1,
+
    .UserBd = BOARD_TYPE_ULT_ULX,
 };