Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47100 )
Change subject: sb/intel/bd82x6x: Use common AHCI library ......................................................................
sb/intel/bd82x6x: Use common AHCI library
Behaviour before after this patch should be equivalent.
Change-Id: Ib1679197c77c5b32c231fd51dd7465a3ebb1d7bd Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/sata.c 1 file changed, 34 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/47100/1
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 875f3f7..87aa841 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -8,6 +8,7 @@ #include <device/pci_ids.h> #include <option.h> #include <acpi/acpi_sata.h> +#include <southbridge/intel/common/ahci.h> #include <types.h>
#include "chip.h" @@ -113,8 +114,6 @@
/* AHCI */ if (sata_mode == 0) { - u8 *abar; - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); @@ -130,32 +129,42 @@ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
/* Initialize AHCI memory-mapped space */ - abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS - /* Set ISS, if available */ + const uintptr_t ahci_bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "AHCI BAR: %p\n", (void *)ahci_bar); + + union ahci_reg_cap ahci_cap = { + .raw = ahci_read32(ahci_bar, AHCI_REG_CAP), + }; + + ahci_cap.external_sata = 0; /* Should be configurable */ + ahci_cap.enclosure_management = 0; + ahci_cap.port_multiplier = 0; + + ahci_cap.partial_state = 1; + ahci_cap.slumber_state = 1; + ahci_cap.aggressive_link_pm = 1; + ahci_cap.staggered_spinup = 1; + + /* If configured, override ISS */ if (config->sata_interface_speed_support) - { - reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) - << 20; - } - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x0c, config->sata_port_map); - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x24); - reg32 &= ~0x00000002; - write32(abar + 0x24, reg32); + ahci_cap.interface_speed = config->sata_interface_speed_support; + + ahci_write32(ahci_bar, AHCI_REG_CAP, ahci_cap.raw); + + ahci_write_ports_implemented(ahci_bar, config->sata_port_map); + + union ahci_reg_cap_2 ahci_cap_2 = { + .raw = ahci_read32(ahci_bar, AHCI_REG_CAP_2), + }; + + ahci_cap_2.nvm_hci_present = 0; + + ahci_write32(ahci_bar, AHCI_REG_CAP_2, ahci_cap_2.raw); + /* VSP (Vendor Specific Register */ - reg32 = read32(abar + 0xa0); + reg32 = ahci_read32(ahci_bar, 0xa0); reg32 &= ~0x00000005; - write32(abar + 0xa0, reg32); + ahci_write32(ahci_bar, 0xa0, reg32); } else { /* IDE */
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47100
to look at the new patch set (#3).
Change subject: sb/intel/bd82x6x: Use common AHCI library ......................................................................
sb/intel/bd82x6x: Use common AHCI library
Behaviour before after this patch should be equivalent.
Change-Id: Ib1679197c77c5b32c231fd51dd7465a3ebb1d7bd Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/sata.c 1 file changed, 34 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/47100/3
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47100
to look at the new patch set (#4).
Change subject: sb/intel/bd82x6x: Use common AHCI library ......................................................................
sb/intel/bd82x6x: Use common AHCI library
Behaviour before after this patch should be equivalent.
Change-Id: Ib1679197c77c5b32c231fd51dd7465a3ebb1d7bd Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/sata.c 1 file changed, 35 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/47100/4
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47100 )
Change subject: sb/intel/bd82x6x: Use common AHCI library ......................................................................
Patch Set 4: Code-Review+1
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47100 )
Change subject: sb/intel/bd82x6x: Use common AHCI library ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47100/5/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/sata.c:
https://review.coreboot.org/c/coreboot/+/47100/5/src/southbridge/intel/bd82x... PS5, Line 132: const uintptr_t ahci_bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); this should use probe_resource instead
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47100?usp=email )
Change subject: sb/intel/bd82x6x: Use common AHCI library ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
-
Angel Pons (Code Review) -
Frans Hendriks (Code Review)
-
Martin L Roth (Code Review)
-
Patrick Rudolph (Code Review)