Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports - coreboot-gerrit

15 Aug 2020


      Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 )
Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports
......................................................................
Patch Set 25:
...
Patch Set 25: Code-Review+1
LGTM. Are there any interdependencies with any of the other PCIe PM-related settings?
Perhaps that "PcieRpAspm" doesn't disable L1 for a given root port?
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/39538
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8
Gerrit-Change-Number: 39538
Gerrit-PatchSet: 25
Gerrit-Owner: Benjamin Doron benjamin.doron00@gmail.com
Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Benjamin Doron benjamin.doron00@gmail.com
Gerrit-Reviewer: Matt DeVillier matt.devillier@gmail.com
Gerrit-Reviewer: Nico Huber nico.h@gmx.de
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Comment-Date: Sat, 15 Aug 2020 06:26:14 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: No
Gerrit-MessageType: comment