[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Support x32 memory configuration

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87234?usp=email )

Change subject: mb/google/nissa/var/anraggar: Support x32 memory configuration
......................................................................

mb/google/nissa/var/anraggar: Support x32 memory configuration

Use GPP_E19 level to determine whether x32 memory configuration is
supported.

BUG=b:409212348
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Ic401d3db57659c6ced13c123591c1fd82fa9a721
Signed-off-by: Qinghong Zeng 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87234
Tested-by: build bot (Jenkins) 
Reviewed-by: Jayvik Desai 
Reviewed-by: Kapil Porwal 
Reviewed-by: Weimin Wu 
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/anraggar/Makefile.mk
M src/mainboard/google/brya/variants/anraggar/gpio.c
A src/mainboard/google/brya/variants/anraggar/memory.c
4 files changed, 27 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Weimin Wu: Looks good to me, but someone else must approve
  Kapil Porwal: Looks good to me, approved
  Jayvik Desai: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index fd1cf58..c60f22a 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -157,6 +157,7 @@
    select HAVE_WWAN_POWER_SEQUENCE
    select INTEL_GMA_HAVE_VBT
    select CHROMEOS_WIFI_SAR if CHROMEOS
+	select ENFORCE_MEM_CHANNEL_DISABLE

config BOARD_GOOGLE_AURASH
    select BOARD_GOOGLE_BASEBOARD_BRASK
diff --git a/src/mainboard/google/brya/variants/anraggar/Makefile.mk b/src/mainboard/google/brya/variants/anraggar/Makefile.mk
index f41cdfd..efe5002 100644
--- a/src/mainboard/google/brya/variants/anraggar/Makefile.mk
+++ b/src/mainboard/google/brya/variants/anraggar/Makefile.mk
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c

+romstage-y += memory.c
 romstage-y += gpio.c

ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c
index 03507b0..cf16091 100644
--- a/src/mainboard/google/brya/variants/anraggar/gpio.c
+++ b/src/mainboard/google/brya/variants/anraggar/gpio.c
@@ -74,6 +74,9 @@
    /* R7 : DMIC_DATA_1A ==> NC */
    PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG),

+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG),
+
    /* Configure the virtual CNVi Bluetooth I2S GPIO pads */
    /* BT_I2S_BCLK */
    PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
@@ -123,6 +126,8 @@
    PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
    /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
    PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG),
 };

static const struct pad_config romstage_gpio_table[] = {
diff --git a/src/mainboard/google/brya/variants/anraggar/memory.c b/src/mainboard/google/brya/variants/anraggar/memory.c
new file mode 100644
index 0000000..51a7ff5
--- /dev/null
+++ b/src/mainboard/google/brya/variants/anraggar/memory.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E19 High -> One RAM Chip
+	 * GPP_E19 Low  -> Two RAM Chip
+	 */
+	if (gpio_get(GPP_E19)) {
+		/* Disable all other channels except first two on each controller */
+		return (BIT(2) | BIT(3));
+	}
+
+	return 0;
+}