Change in coreboot[master]: vc/mediatek/mt8195: Improve DRAM driver

[Rex-BC Chen (Code Review)]

Attention is currently required from: Ryan Chuang.
Hello Ryan Chuang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/56099

to review the following change.

Change subject: vc/mediatek/mt8195: Improve DRAM driver
......................................................................

vc/mediatek/mt8195: Improve DRAM driver

1. Improve settings of duty calibration.
2. Enable VREF calibration at DDR3200 for enter/exit S0 stability.
3. Enable DRAM Vcore DVFS settings.

Signed-off-by: Ryan Chuang 
Change-Id: I8ae81bf26e3665e595721577794836ef39b55ef7
---
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
M src/vendorcode/mediatek/mt8195/dramc/dramc_top.c
M src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
4 files changed, 14 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/56099/1

diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
index cea83a0..286e9a0 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
@@ -14804,9 +14804,15 @@
 #endif
 #endif
     {
+        U8 u1ChannelIdx;
+        U8 u1backup_channel = vGetPHY2ChannelMapping(p);
+
         #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
         if(p->femmc_Ready==1)
         {
+            for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++){
+                vSetPHY2ChannelMapping(p, u1ChannelIdx);
+
             DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]);
             DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]);
             #if __LP5_COMBO__
@@ -14816,6 +14822,8 @@
             DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM);
             DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ);
             #endif
+            }
+            vSetPHY2ChannelMapping(p, u1backup_channel);

vSetCalibrationResult(p, DRAM_CALIBRATION_DUTY_SCAN, DRAM_FAST_K);
             return;
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
index 71415d2..632a176 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
@@ -33,7 +33,7 @@
 u8 ett_fix_freq = 0xff; // 0xFF=all freq by gFreqTbl. The 0x"X" != 0xFF for single freq by gFreqTbl index, ex: 0x3 for DDR3733

DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = {
-    {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K,  VREF_CALI_OFF,  CLOSE_LOOP_MODE},  // highest freq of term group (3733) must k first.
+    {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K,  VREF_CALI_ON,  CLOSE_LOOP_MODE},  // highest freq of term group (3733) must k first.
     {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K,  VREF_CALI_ON,   CLOSE_LOOP_MODE},  // highest freq of term group (3733) must k first.
 #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
     {LP4_DDR400  /*2*/, DIV4_MODE, SRAM_SHU7, DUTY_DEFAULT, VREF_CALI_OFF,  OPEN_LOOP_MODE},
@@ -272,7 +272,7 @@

#ifndef DDR_INIT_TIME_PROFILING
     print("Read voltage for %d, %d\n", p->frequency, vGet_Current_SRAMIdx(p));
-    print("Vio18 = %d\n", dramc_get_vio18_voltage());
+    //print("Vio18 = %d\n", dramc_get_vio18_voltage());
     print("Vcore = %d\n", dramc_get_vcore_voltage());
     print("Vdram = %d\n", dramc_get_vmdd_voltage(p->dram_type));
     print("Vddq = %d\n", dramc_get_vmddq_voltage(p->dram_type));
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c
index 1595073..87a6040 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c
@@ -352,6 +352,9 @@
 {
 #ifdef MTK_PMIC_MT6359
    return mtk_regulator_set_voltage(&reg_vcore, vcore, MAX_VCORE);
+#elif CONFIG(CHROMEOS)
+	dramc_debug("%s set vcore to %d\n", __func__, vcore);
+	mainboard_set_regulator_vol(MTK_REGULATOR_VCORE, vcore);
 #endif
    return 0;
 }
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h b/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
index a40f290..d27d7ea 100644
--- a/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
@@ -123,7 +123,7 @@
 #else
 #define ENABLE_EYESCAN_GRAPH 1
 #endif
-#define EYESCAN_GRAPH_CATX_VREF_STEP 1  // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868
+#define EYESCAN_GRAPH_CATX_VREF_STEP 0x1U  // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868
 #define EYESCAN_GRAPH_RX_VREF_STEP 2
 #define EYESCAN_RX_VREF_RANGE_END 128   //field is 6 bit, but can only use 0~63,7bit ->127
 #define EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF    10