Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36637 )
Change subject: arch/x86: Drop some __SMM__ guards ......................................................................
arch/x86: Drop some __SMM__ guards
Change-Id: I64063bbae5b44f1f24566609a7f770c6d5f69fac Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/model_206ax.h M src/include/cpu/x86/smm.h M src/mainboard/google/stout/ec.h M src/mainboard/hp/pavilion_m6_1035dx/ec.h M src/mainboard/lenovo/g505s/ec.h M src/mainboard/lenovo/s230u/ec.h M src/northbridge/intel/nehalem/nehalem.h M src/northbridge/intel/sandybridge/sandybridge.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/intel/broadwell/include/soc/xhci.h M src/southbridge/amd/agesa/hudson/smi.h M src/southbridge/amd/pi/hudson/smi.h 15 files changed, 5 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/36637/1
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 53a77a9..94fb3f1 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -81,12 +81,9 @@ #define PSS_LATENCY_BUSMASTER 10
#ifndef __ROMCC__ -#ifdef __SMM__ /* Lock MSRs */ void intel_model_406dx_finalize_smm(void); -#else int cpu_config_tdp_levels(void); #endif -#endif
#endif /* _CPU_INTEL_MODEL_406DX_H */ diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 8087edb..f6982d9 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -69,14 +69,12 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10
-#ifdef __SMM__ /* Lock MSRs */ void intel_model_2065x_finalize_smm(void); -#else + /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -#endif
/* Sanity check config options. */ #if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index f2a0b71..7017c12 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -93,14 +93,12 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif
-#ifdef __SMM__ /* Lock MSRs */ void intel_model_206ax_finalize_smm(void); -#else + /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -#endif int get_platform_id(void);
#endif diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index d8b9efe..cf107b1 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -86,7 +86,6 @@ /* smm_handler_t is called with arg of smm_module_params pointer. */ typedef asmlinkage void (*smm_handler_t)(void *);
-#ifdef __SMM__ /* SMM Runtime helpers. */
/* Entry point for SMM modules. */ @@ -95,7 +94,6 @@ /* Retrieve SMM save state for a given CPU. WARNING: This does not take into * account CPUs which are configured to not save their state to RAM. */ void *smm_get_save_state(int cpu); -#endif /* __SMM__ */
/* SMM Module Loading API */
diff --git a/src/mainboard/google/stout/ec.h b/src/mainboard/google/stout/ec.h index 8c7882f..f035e24 100644 --- a/src/mainboard/google/stout/ec.h +++ b/src/mainboard/google/stout/ec.h @@ -22,10 +22,7 @@ #define EC_SMI_LID_CLOSED 0x2B
#ifndef __ACPI__ -extern void stout_ec_init(void); -#endif - -#ifdef __SMM__ +void stout_ec_init(void); void stout_ec_finalize_smm(void); #endif
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.h b/src/mainboard/hp/pavilion_m6_1035dx/ec.h index 40e33ee..5567251 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.h @@ -19,8 +19,6 @@
#include "mainboard.h"
-#ifndef __SMM__ void pavilion_m6_1035dx_ec_init(void); -#endif
#endif /* _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H */ diff --git a/src/mainboard/lenovo/g505s/ec.h b/src/mainboard/lenovo/g505s/ec.h index 86fd673..52a3ab7 100644 --- a/src/mainboard/lenovo/g505s/ec.h +++ b/src/mainboard/lenovo/g505s/ec.h @@ -19,8 +19,6 @@
#include "mainboard.h"
-#ifndef __SMM__ void lenovo_g505s_ec_init(void); -#endif
#endif /* _MAINBOARD_LENOVO_G505S_EC_H */ diff --git a/src/mainboard/lenovo/s230u/ec.h b/src/mainboard/lenovo/s230u/ec.h index 87fbc7f..a5bc423 100644 --- a/src/mainboard/lenovo/s230u/ec.h +++ b/src/mainboard/lenovo/s230u/ec.h @@ -17,9 +17,7 @@ #ifndef _MAINBOARD_LENOVO_S230U_EC_H #define _MAINBOARD_LENOVO_S230U_EC_H
-#ifndef __SMM__ void lenovo_s230u_ec_init(void); -#endif
#define ECMM(x) (*((volatile u8 *)(CONFIG_EC_BASE_ADDRESS + x))) #define ec_mm_read(addr) (ECMM(0x100 + addr)) diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index ebec63d..493c5b1 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -249,17 +249,14 @@ #define PCI_DEVICE_ID_SB 0x0104 #define PCI_DEVICE_ID_IB 0x0154
-#ifdef __SMM__ void intel_nehalem_finalize_smm(void); -#else /* !__SMM__ */ + int bridge_silicon_revision(void); void nehalem_early_initialization(int chipset_type); void nehalem_late_initialization(void); void mainboard_pre_raminit(void); void mainboard_get_spd_map(u8 *spd_addrmap);
-#endif /* !__SMM__ */ - #endif #endif #endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8664c5d..31d4358 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -203,9 +203,8 @@
#ifndef __ASSEMBLER__
-#ifdef __SMM__ void intel_sandybridge_finalize_smm(void); -#else /* !__SMM__ */ + int bridge_silicon_revision(void); void systemagent_early_init(void); void sandybridge_init_iommu(void); @@ -213,8 +212,6 @@ void northbridge_romstage_finalize(int s3resume); void early_init_dmi(void);
-#endif /* !__SMM__ */ - void pch_enable_lpc(void); void mainboard_early_init(int s3resume); void mainboard_config_superio(void); diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index 66c2050..e7f9da6 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -232,8 +232,6 @@ void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event);
-#ifndef __SMM__ void enable_smi_generation(void); -#endif
#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 000eed8..5301dd7 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -235,8 +235,6 @@ void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event);
-#ifndef __SMM__ void enable_smi_generation(void); -#endif
#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */ diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h index 33e4c2d..87a5934 100644 --- a/src/soc/intel/broadwell/include/soc/xhci.h +++ b/src/soc/intel/broadwell/include/soc/xhci.h @@ -50,8 +50,6 @@ #define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
-#ifdef __SMM__ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); -#endif
#endif diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index d1594f3..5e0c09a 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -71,8 +71,6 @@ void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void);
-#ifndef __SMM__ void hudson_enable_smi_generation(void); -#endif
#endif /* _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H */ diff --git a/src/southbridge/amd/pi/hudson/smi.h b/src/southbridge/amd/pi/hudson/smi.h index dde9d6e..684dca5 100644 --- a/src/southbridge/amd/pi/hudson/smi.h +++ b/src/southbridge/amd/pi/hudson/smi.h @@ -71,8 +71,6 @@ void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void);
-#ifndef __SMM__ void hudson_enable_smi_generation(void); -#endif
#endif /* _SOUTHBRIDGE_AMD_PI_HUDSON_SMI_H */
Hello Alexander Couzens, Aaron Durbin, Patrick Rudolph, build bot (Jenkins), Furquan Shaikh, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36637
to look at the new patch set (#3).
Change subject: arch/x86: Drop some __SMM__ guards ......................................................................
arch/x86: Drop some __SMM__ guards
Change-Id: I64063bbae5b44f1f24566609a7f770c6d5f69fac Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/model_206ax.h M src/include/cpu/x86/smm.h M src/mainboard/google/stout/ec.h M src/mainboard/hp/pavilion_m6_1035dx/ec.h M src/mainboard/lenovo/g505s/ec.h M src/mainboard/lenovo/s230u/ec.h M src/northbridge/intel/nehalem/nehalem.h M src/northbridge/intel/sandybridge/sandybridge.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/xhci.h M src/soc/intel/denverton_ns/include/soc/nvs.h M src/soc/intel/fsp_baytrail/include/soc/nvs.h M src/southbridge/amd/agesa/hudson/smi.h M src/southbridge/amd/pi/hudson/smi.h M src/southbridge/intel/bd82x6x/nvs.h M src/southbridge/intel/fsp_rangeley/nvs.h M src/southbridge/intel/ibexpeak/nvs.h M src/southbridge/intel/lynxpoint/nvs.h 24 files changed, 10 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/36637/3
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36637 )
Change subject: arch/x86: Drop some __SMM__ guards ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36637 )
Change subject: arch/x86: Drop some __SMM__ guards ......................................................................
arch/x86: Drop some __SMM__ guards
Change-Id: I64063bbae5b44f1f24566609a7f770c6d5f69fac Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36637 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/model_206ax.h M src/include/cpu/x86/smm.h M src/mainboard/google/stout/ec.h M src/mainboard/hp/pavilion_m6_1035dx/ec.h M src/mainboard/lenovo/g505s/ec.h M src/mainboard/lenovo/s230u/ec.h M src/northbridge/intel/nehalem/nehalem.h M src/northbridge/intel/sandybridge/sandybridge.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/xhci.h M src/soc/intel/denverton_ns/include/soc/nvs.h M src/soc/intel/fsp_baytrail/include/soc/nvs.h M src/southbridge/amd/agesa/hudson/smi.h M src/southbridge/amd/pi/hudson/smi.h M src/southbridge/intel/bd82x6x/nvs.h M src/southbridge/intel/fsp_rangeley/nvs.h M src/southbridge/intel/ibexpeak/nvs.h M src/southbridge/intel/lynxpoint/nvs.h 24 files changed, 10 insertions(+), 57 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 140dc2e..adfec56 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -79,12 +79,9 @@ #define PSS_LATENCY_BUSMASTER 10
#ifndef __ROMCC__ -#ifdef __SMM__ /* Lock MSRs */ void intel_model_406dx_finalize_smm(void); -#else int cpu_config_tdp_levels(void); #endif -#endif
#endif /* _CPU_INTEL_MODEL_406DX_H */ diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 8087edb..f6982d9 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -69,14 +69,12 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10
-#ifdef __SMM__ /* Lock MSRs */ void intel_model_2065x_finalize_smm(void); -#else + /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -#endif
/* Sanity check config options. */ #if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index f2a0b71..7017c12 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -93,14 +93,12 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif
-#ifdef __SMM__ /* Lock MSRs */ void intel_model_206ax_finalize_smm(void); -#else + /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -#endif int get_platform_id(void);
#endif diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index d8b9efe..cf107b1 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -86,7 +86,6 @@ /* smm_handler_t is called with arg of smm_module_params pointer. */ typedef asmlinkage void (*smm_handler_t)(void *);
-#ifdef __SMM__ /* SMM Runtime helpers. */
/* Entry point for SMM modules. */ @@ -95,7 +94,6 @@ /* Retrieve SMM save state for a given CPU. WARNING: This does not take into * account CPUs which are configured to not save their state to RAM. */ void *smm_get_save_state(int cpu); -#endif /* __SMM__ */
/* SMM Module Loading API */
diff --git a/src/mainboard/google/stout/ec.h b/src/mainboard/google/stout/ec.h index 8c7882f..f035e24 100644 --- a/src/mainboard/google/stout/ec.h +++ b/src/mainboard/google/stout/ec.h @@ -22,10 +22,7 @@ #define EC_SMI_LID_CLOSED 0x2B
#ifndef __ACPI__ -extern void stout_ec_init(void); -#endif - -#ifdef __SMM__ +void stout_ec_init(void); void stout_ec_finalize_smm(void); #endif
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.h b/src/mainboard/hp/pavilion_m6_1035dx/ec.h index 40e33ee..5567251 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.h @@ -19,8 +19,6 @@
#include "mainboard.h"
-#ifndef __SMM__ void pavilion_m6_1035dx_ec_init(void); -#endif
#endif /* _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H */ diff --git a/src/mainboard/lenovo/g505s/ec.h b/src/mainboard/lenovo/g505s/ec.h index 86fd673..52a3ab7 100644 --- a/src/mainboard/lenovo/g505s/ec.h +++ b/src/mainboard/lenovo/g505s/ec.h @@ -19,8 +19,6 @@
#include "mainboard.h"
-#ifndef __SMM__ void lenovo_g505s_ec_init(void); -#endif
#endif /* _MAINBOARD_LENOVO_G505S_EC_H */ diff --git a/src/mainboard/lenovo/s230u/ec.h b/src/mainboard/lenovo/s230u/ec.h index 87fbc7f..a5bc423 100644 --- a/src/mainboard/lenovo/s230u/ec.h +++ b/src/mainboard/lenovo/s230u/ec.h @@ -17,9 +17,7 @@ #ifndef _MAINBOARD_LENOVO_S230U_EC_H #define _MAINBOARD_LENOVO_S230U_EC_H
-#ifndef __SMM__ void lenovo_s230u_ec_init(void); -#endif
#define ECMM(x) (*((volatile u8 *)(CONFIG_EC_BASE_ADDRESS + x))) #define ec_mm_read(addr) (ECMM(0x100 + addr)) diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index ebec63d..493c5b1 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -249,17 +249,14 @@ #define PCI_DEVICE_ID_SB 0x0104 #define PCI_DEVICE_ID_IB 0x0154
-#ifdef __SMM__ void intel_nehalem_finalize_smm(void); -#else /* !__SMM__ */ + int bridge_silicon_revision(void); void nehalem_early_initialization(int chipset_type); void nehalem_late_initialization(void); void mainboard_pre_raminit(void); void mainboard_get_spd_map(u8 *spd_addrmap);
-#endif /* !__SMM__ */ - #endif #endif #endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8664c5d..31d4358 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -203,9 +203,8 @@
#ifndef __ASSEMBLER__
-#ifdef __SMM__ void intel_sandybridge_finalize_smm(void); -#else /* !__SMM__ */ + int bridge_silicon_revision(void); void systemagent_early_init(void); void sandybridge_init_iommu(void); @@ -213,8 +212,6 @@ void northbridge_romstage_finalize(int s3resume); void early_init_dmi(void);
-#endif /* !__SMM__ */ - void pch_enable_lpc(void); void mainboard_early_init(int s3resume); void mainboard_config_superio(void); diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index 66c2050..e7f9da6 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -232,8 +232,6 @@ void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event);
-#ifndef __SMM__ void enable_smi_generation(void); -#endif
#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 000eed8..5301dd7 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -235,8 +235,6 @@ void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event);
-#ifndef __SMM__ void enable_smi_generation(void); -#endif
#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */ diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 08ccbf4..4a89eb9 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -104,9 +104,8 @@ check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs); -#ifdef __SMM__ + /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif
#endif /* _BAYTRAIL_NVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index d2dc706..33800ef 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -107,9 +107,7 @@ check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs); -#if ENV_SMM /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif
#endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 63c7bde..456fda6 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -96,9 +96,8 @@ check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs); -#ifdef __SMM__ + /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif
#endif diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h index 33e4c2d..87a5934 100644 --- a/src/soc/intel/broadwell/include/soc/xhci.h +++ b/src/soc/intel/broadwell/include/soc/xhci.h @@ -50,8 +50,6 @@ #define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
-#ifdef __SMM__ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); -#endif
#endif diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h index 5a94b24..8d1bc6a 100644 --- a/src/soc/intel/denverton_ns/include/soc/nvs.h +++ b/src/soc/intel/denverton_ns/include/soc/nvs.h @@ -65,9 +65,7 @@
} __packed global_nvs_t;
-#ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif
#endif /* _DENVERTON_NS_NVS_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/nvs.h b/src/soc/intel/fsp_baytrail/include/soc/nvs.h index d42763a..df2fc60 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/nvs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/nvs.h @@ -65,9 +65,8 @@ } __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs); -#ifdef __SMM__ + /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif
#endif /* _BAYTRAIL_NVS_H_ */ diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index d1594f3..5e0c09a 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -71,8 +71,6 @@ void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void);
-#ifndef __SMM__ void hudson_enable_smi_generation(void); -#endif
#endif /* _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H */ diff --git a/src/southbridge/amd/pi/hudson/smi.h b/src/southbridge/amd/pi/hudson/smi.h index dde9d6e..684dca5 100644 --- a/src/southbridge/amd/pi/hudson/smi.h +++ b/src/southbridge/amd/pi/hudson/smi.h @@ -71,8 +71,6 @@ void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void);
-#ifndef __SMM__ void hudson_enable_smi_generation(void); -#endif
#endif /* _SOUTHBRIDGE_AMD_PI_HUDSON_SMI_H */ diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 6558511..a6b0bdb 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -155,8 +155,6 @@ } __packed global_nvs_t; check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-#ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif void acpi_create_gnvs(global_nvs_t *gnvs); diff --git a/src/southbridge/intel/fsp_rangeley/nvs.h b/src/southbridge/intel/fsp_rangeley/nvs.h index 12de769..47fca68 100644 --- a/src/southbridge/intel/fsp_rangeley/nvs.h +++ b/src/southbridge/intel/fsp_rangeley/nvs.h @@ -146,7 +146,6 @@ } __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs); -#ifdef __SMM__ + /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 36db12c..a956398 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -153,8 +153,7 @@ } __packed global_nvs_t; check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-#ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif + void acpi_create_gnvs(global_nvs_t *gnvs); diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index a8f0dea..3aca7bb 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -130,9 +130,7 @@ } __packed global_nvs_t; check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-#ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif
void acpi_create_gnvs(global_nvs_t * gnvs);
-
Kyösti Mälkki (Code Review) -
Patrick Georgi (Code Review)