[S] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal.

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69571 )

Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL
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Patch Set 2:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/69571/comment/f161bfcd_0495405c 
PS2, Line 9: The patch logs CSE RO's write protection information for Alder Lake
Meteor

https://review.coreboot.org/c/coreboot/+/69571/comment/88d58fd2_720fc4ba 
PS2, Line 21: YES
How did you test this? Did you enable SPI protection through MFIT and test the coreboot on Rex?

File src/soc/intel/meteorlake/me.c:

https://review.coreboot.org/c/coreboot/+/69571/comment/c685a5b6_a0b5ae79 
PS2, Line 186: hfsts1.fields.mfg_mode
mfg_mode alone doesn't represent the end of manufacturing status. Please refer patch:https://review.coreboot.org/c/coreboot/+/69324 for reference