Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38772 )
Change subject: mb/google/dedede: Enable AP <-> H1 Communication ......................................................................
mb/google/dedede: Enable AP <-> H1 Communication
Turn on the H1 device in the devicetree. Configure the concerned GPIOs and enable the required config items.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I37972635454cd0d35608623e7be4110012ace658 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 3 files changed, 54 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/38772/1
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 5254d16..9b5bd4a 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,11 +1,14 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n + select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_TPM2 select SOC_INTEL_JASPERLAKE
if BOARD_GOOGLE_BASEBOARD_DEDEDE @@ -25,6 +28,9 @@ string default "variants/baseboard/devicetree.cb"
+config DRIVER_TPM_SPI_BUS + default 0x1 + config MAINBOARD_DIR string default "google/dedede" @@ -41,6 +47,10 @@ int default 4
+config TPM_TIS_ACPI_INTERRUPT + int + default 4 # GPE0_DW0_4 (GPP_B4) + config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 44d9ca2..0cf696c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -19,6 +19,22 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_H"
+ # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device @@ -54,7 +70,14 @@ device pci 1c.7 off end # PCI Express Root Port 8 device pci 1e.0 off end # UART 0 device pci 1e.1 off end # UART 1 - device pci 1e.2 off end # GSPI 0 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)" + device spi 0 on end + end + end # GSPI 0 device pci 1e.3 off end # GSPI 1 device pci 1f.0 on chip ec/google/chromeec diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 0908412..fc63ffe 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -21,11 +21,30 @@ /* A4 : ESPI_CS# */ /* A5 : ESPI_CLK */ /* A6 : ESPI_RESET_L */ + /* B4 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), };
/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* ToDo: Fill early gpio configuration */ + /* B4 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), };
const struct pad_config *__weak variant_gpio_table(size_t *num)
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38772 )
Change subject: mb/google/dedede: Enable AP <-> H1 Communication ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38772/1/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/38772/1/src/mainboard/google/dedede... PS1, Line 25: PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/38772/1/src/mainboard/google/dedede... PS1, Line 25: PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/38772/1/src/mainboard/google/dedede... PS1, Line 39: PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/38772/1/src/mainboard/google/dedede... PS1, Line 39: PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), please, no spaces at the start of a line
Karthik Ramasubramanian has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/38772 )
Change subject: mb/google/dedede: Enable AP <-> H1 Communication ......................................................................
mb/google/dedede: Enable AP <-> H1 Communication
Turn on the H1 device in the devicetree. Configure the concerned GPIOs and enable the required config items.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I37972635454cd0d35608623e7be4110012ace658 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 3 files changed, 54 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/38772/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38772 )
Change subject: mb/google/dedede: Enable AP <-> H1 Communication ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38772/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38772/2/src/mainboard/google/dedede... PS2, Line 73: on In addition to this, you also need to set SerialIoDevMode FSP UPD to ensure that FSP keeps the controller enabled.
Hello Justin TerAvest, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38772
to look at the new patch set (#3).
Change subject: mb/google/dedede: Enable AP <-> H1 Communication ......................................................................
mb/google/dedede: Enable AP <-> H1 Communication
Turn on the H1 device in the devicetree. Configure the concerned GPIOs and enable the required config items.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I37972635454cd0d35608623e7be4110012ace658 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 3 files changed, 57 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/38772/3
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38772 )
Change subject: mb/google/dedede: Enable AP <-> H1 Communication ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38772/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38772/2/src/mainboard/google/dedede... PS2, Line 73: on
In addition to this, you also need to set SerialIoDevMode FSP UPD to ensure that FSP keeps the contr […]
Done
Justin TerAvest has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38772 )
Change subject: mb/google/dedede: Enable AP <-> H1 Communication ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38772 )
Change subject: mb/google/dedede: Enable AP <-> H1 Communication ......................................................................
mb/google/dedede: Enable AP <-> H1 Communication
Turn on the H1 device in the devicetree. Configure the concerned GPIOs and enable the required config items.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I37972635454cd0d35608623e7be4110012ace658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38772 Reviewed-by: Justin TerAvest teravest@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 3 files changed, 57 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Justin TerAvest: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 5254d16..9b5bd4a 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,11 +1,14 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n + select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_TPM2 select SOC_INTEL_JASPERLAKE
if BOARD_GOOGLE_BASEBOARD_DEDEDE @@ -25,6 +28,9 @@ string default "variants/baseboard/devicetree.cb"
+config DRIVER_TPM_SPI_BUS + default 0x1 + config MAINBOARD_DIR string default "google/dedede" @@ -41,6 +47,10 @@ int default 4
+config TPM_TIS_ACPI_INTERRUPT + int + default 4 # GPE0_DW0_4 (GPP_B4) + config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2a0b760..e98b686 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -29,13 +29,13 @@ }"
register "SerialIoGSpiMode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, }"
register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI0] = 1, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, }" @@ -52,6 +52,22 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }"
+ # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device @@ -87,7 +103,14 @@ device pci 1c.7 off end # PCI Express Root Port 8 device pci 1e.0 off end # UART 0 device pci 1e.1 off end # UART 1 - device pci 1e.2 off end # GSPI 0 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)" + device spi 0 on end + end + end # GSPI 0 device pci 1e.3 off end # GSPI 1 device pci 1f.0 on chip ec/google/chromeec diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 0908412..b9d77bf 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -21,11 +21,31 @@ /* A4 : ESPI_CS# */ /* A5 : ESPI_CLK */ /* A6 : ESPI_RESET_L */ + + /* B4 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), };
/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* ToDo: Fill early gpio configuration */ + /* B4 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), };
const struct pad_config *__weak variant_gpio_table(size_t *num)
-
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