Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybride storage mode ......................................................................
mb/intel/tglrvp: Enable Hybride storage mode
BUG=b:148604250 BRANCH=none TEST=Build and test booting TGLRVP form NVMe and Optane Check Pcie lane configuration Show all the NVMe devices lspci -d ::0108 Show all the NVMe devices and be really verbose lspci -vvvd ::0108 Print PCIe lane capabilities and configurations for all the NVMe devices. lspci -vvvd ::0108 | grep -e x[124] Print all the PCIe information of the device ae:00.0 lspci -vvvs ae:
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39233/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index d4b5a39..0a1e6f6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -37,6 +37,9 @@ register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1"
+ # Hybride storage mode + register "HybridStorageMode" = "1" + register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcClkReq[3]" = "3"
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybride storage mode ......................................................................
Patch Set 2: Code-Review+1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybride storage mode ......................................................................
Patch Set 3:
Rebased with new UPD header
caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybride storage mode ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39233/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
PS3: enable on UP4 as well?
may need to coordinate with https://review.coreboot.org/c/coreboot/+/39363
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybride storage mode ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39233/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
PS3:
enable on UP4 as well? […]
Yes. it need to enabled in UP4. But not added in UP4 patches( https://review.coreboot.org/c/coreboot/+/39363) for reducing inter dependencies. Expecting https://review.coreboot.org/c/coreboot/+/39363 merged first and I'll update this patch to enable UP4.
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Nick Vaccaro, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39233
to look at the new patch set (#4).
Change subject: mb/intel/tglrvp: Enable Hybride storage mode ......................................................................
mb/intel/tglrvp: Enable Hybride storage mode
BUG=b:148604250 BRANCH=none TEST=Build and test booting TGLRVP form NVMe and Optane Check Pcie lane configuration Show all the NVMe devices lspci -d ::0108 Show all the NVMe devices and be really verbose lspci -vvvd ::0108 Print PCIe lane capabilities and configurations for all the NVMe devices. lspci -vvvd ::0108 | grep -e x[124] Print all the PCIe information of the device ae:00.0 lspci -vvvs ae:
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39233/4
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybride storage mode ......................................................................
Patch Set 4: Code-Review+1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybride storage mode ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39233/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
PS3:
Yes. it need to enabled in UP4. But not added in UP4 patches( https://review.coreboot. […]
Add Enabling UP4 change as UP4 patches are merged
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybride storage mode ......................................................................
Patch Set 4: Code-Review+1
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybride storage mode ......................................................................
Patch Set 4: Code-Review+2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybride storage mode ......................................................................
Patch Set 4: Code-Review+2
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybride storage mode ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39233/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39233/4//COMMIT_MSG@7 PS4, Line 7: Hybride Hybrid
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Nick Vaccaro, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39233
to look at the new patch set (#5).
Change subject: mb/intel/tglrvp: Enable Hybrid storage mode ......................................................................
mb/intel/tglrvp: Enable Hybrid storage mode
BUG=b:148604250 BRANCH=none TEST=Build and test booting TGLRVP form NVMe and Optane Check Pcie lane configuration Show all the NVMe devices lspci -d ::0108 Show all the NVMe devices and be really verbose lspci -vvvd ::0108 Print PCIe lane capabilities and configurations for all the NVMe devices. lspci -vvvd ::0108 | grep -e x[124] Print all the PCIe information of the device ae:00.0 lspci -vvvs ae:
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39233/5
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybrid storage mode ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39233/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39233/4//COMMIT_MSG@7 PS4, Line 7: Hybride
Hybrid
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybrid storage mode ......................................................................
Patch Set 5: Code-Review+1
(3 comments)
Ooone last thing
https://review.coreboot.org/c/coreboot/+/39233/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39233/5//COMMIT_MSG@12 PS5, Line 12: Pcie PCIe
https://review.coreboot.org/c/coreboot/+/39233/5/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39233/5/src/mainboard/intel/tglrvp/... PS5, Line 40: Hybride trailing `e`, should be `Hybrid`
https://review.coreboot.org/c/coreboot/+/39233/5/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39233/5/src/mainboard/intel/tglrvp/... PS5, Line 40: Hybride trailing `e`, should be `Hybrid`
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Angel Pons, Nick Vaccaro, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39233
to look at the new patch set (#6).
Change subject: mb/intel/tglrvp: Enable Hybrid storage mode ......................................................................
mb/intel/tglrvp: Enable Hybrid storage mode
BUG=b:148604250 BRANCH=none TEST=Build and test booting TGLRVP form NVMe and Optane Check Pcie lane configuration Show all the NVMe devices lspci -d ::0108 Show all the NVMe devices and be really verbose lspci -vvvd ::0108 Print PCIe lane capabilities and configurations for all the NVMe devices. lspci -vvvd ::0108 | grep -e x[124] Print all the PCIe information of the device ae:00.0 lspci -vvvs ae:
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39233/6
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Angel Pons, Nick Vaccaro, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39233
to look at the new patch set (#7).
Change subject: mb/intel/tglrvp: Enable Hybrid storage mode ......................................................................
mb/intel/tglrvp: Enable Hybrid storage mode
BUG=b:148604250 BRANCH=none TEST=Build and test booting TGLRVP form NVMe and Optane Check PCIe lane configuration Show all the NVMe devices lspci -d ::0108 Show all the NVMe devices and be really verbose lspci -vvvd ::0108 Print PCIe lane capabilities and configurations for all the NVMe devices. lspci -vvvd ::0108 | grep -e x[124] Print all the PCIe information of the device ae:00.0 lspci -vvvs ae:
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39233/7
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybrid storage mode ......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39233/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39233/5//COMMIT_MSG@12 PS5, Line 12: Pcie
PCIe
Ack
https://review.coreboot.org/c/coreboot/+/39233/5/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39233/5/src/mainboard/intel/tglrvp/... PS5, Line 40: Hybride
trailing `e`, should be `Hybrid`
Ack
https://review.coreboot.org/c/coreboot/+/39233/5/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39233/5/src/mainboard/intel/tglrvp/... PS5, Line 40: Hybride
trailing `e`, should be `Hybrid`
Ack
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybrid storage mode ......................................................................
Patch Set 7: Code-Review+1
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybrid storage mode ......................................................................
Patch Set 8: Code-Review+1
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybrid storage mode ......................................................................
Patch Set 8: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39233 )
Change subject: mb/intel/tglrvp: Enable Hybrid storage mode ......................................................................
mb/intel/tglrvp: Enable Hybrid storage mode
BUG=b:148604250 BRANCH=none TEST=Build and test booting TGLRVP form NVMe and Optane Check PCIe lane configuration Show all the NVMe devices lspci -d ::0108 Show all the NVMe devices and be really verbose lspci -vvvd ::0108 Print PCIe lane capabilities and configurations for all the NVMe devices. lspci -vvvd ::0108 | grep -e x[124] Print all the PCIe information of the device ae:00.0 lspci -vvvs ae:
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39233 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Srinidhi N Kaushik: Looks good to me, approved Caveh Jalali: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index e60e648..4492acb 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -37,6 +37,9 @@ register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1"
+ # Hybrid storage mode + register "HybridStorageMode" = "1" + register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcClkReq[3]" = "3" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 1f05e0e..643db36 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -37,6 +37,9 @@ register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1"
+ # Hybrid storage mode + register "HybridStorageMode" = "1" + register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcClkReq[3]" = "3"
-
Angel Pons (Code Review) -
Caveh Jalali (Code Review)
-
caveh jalali (Code Review)
-
Nick Vaccaro (Code Review)
-
Patrick Georgi (Code Review)
-
Srinidhi N Kaushik (Code Review)
-
Wonkyu Kim (Code Review)