Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPD ......................................................................
mb/google/volteer: fix incorrect fields in SPD
According to Intel Document #616599, 1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10 columns) 2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel x16)
This change fixes those two values in the existing SPD files for Volteer.
BUG=b:152827558 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Volteer to kernel.
Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40242/1
diff --git a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex index a94b41a..94f258e 100644 --- a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex +++ b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex @@ -1,4 +1,4 @@ -23 11 11 0E 15 19 95 08 00 00 00 00 02 21 00 00 +23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex index 7ef8220..ad77100 100644 --- a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex +++ b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex @@ -1,4 +1,4 @@ -23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 48 00 04 00 92 54 05 00 87 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Nick Vaccaro has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
mb/google/volteer: fix incorrect fields in SPDs
According to Intel Document #616599, 1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10 columns) 2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel x16)
This change fixes those two values in the existing SPD files for Volteer.
BUG=b:152827558 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Volteer to kernel.
Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40242/2
Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40242
to look at the new patch set (#3).
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
mb/google/volteer: fix incorrect fields in SPDs
According to Intel Document #616599, 1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10 columns) 2) SPD byte offset #13 should be "0x01" (1 channel x16)
This change fixes those two values in the existing SPD files for Volteer.
BUG=b:152827558 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Volteer to kernel.
Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40242/3
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
Patch Set 3: Code-Review+1
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40242/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex:
https://review.coreboot.org/c/coreboot/+/40242/3/src/mainboard/google/voltee... PS3, Line 1: 40 isn't this the Post Package Repair "supported" bit? i kinda doubt the MRC cares about this value.
Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40242
to look at the new patch set (#4).
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
mb/google/volteer: fix incorrect fields in SPDs
According to Intel Document #616599, 1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10 columns) 2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel x16)
This change fixes those two values in the existing SPD files for Volteer.
BUG=b:152827558 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Volteer to kernel.
Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40242/4
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40242/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex:
https://review.coreboot.org/c/coreboot/+/40242/3/src/mainboard/google/voltee... PS3, Line 1: 40
isn't this the Post Package Repair "supported" bit? […]
Good catch, that is one of the generic fields that should be zero'd out.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
Patch Set 4:
(1 comment)
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40242/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex:
https://review.coreboot.org/c/coreboot/+/40242/3/src/mainboard/google/voltee... PS3, Line 1: 40
Good catch, that is one of the generic fields that should be zero'd out.
resolved
Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40242
to look at the new patch set (#5).
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
mb/google/volteer: fix incorrect fields in SPDs
According to Intel Document #616599, 1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10 columns) 2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel x16)
This change fixes those two values in the existing SPD files for Volteer.
BUG=b:152827558 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Volteer to kernel.
Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40242/5
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
Patch Set 5: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40242/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex:
https://review.coreboot.org/c/coreboot/+/40242/5/src/mainboard/google/voltee... PS5, Line 1: 00 This change is not captured in the commit message.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
Patch Set 5: Code-Review+1
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
Patch Set 5: -Code-Review
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40242/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex:
https://review.coreboot.org/c/coreboot/+/40242/5/src/mainboard/google/voltee... PS5, Line 1: 00
This change is not captured in the commit message.
done
Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Paul Menzel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40242
to look at the new patch set (#6).
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
mb/google/volteer: fix incorrect fields in SPDs
According to Intel Document #616599, 1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10 columns) 2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel x16)
This change fixes those two values in the existing SPD files for Volteer, and zero'd byte 9 (bytes 8-11 should be zero'd in a generic SPD).
BUG=b:152827558 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Volteer to kernel.
Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40242/6
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40242/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40242/6//COMMIT_MSG@16 PS6, Line 16: zero'd zero’s ?
Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Paul Menzel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40242
to look at the new patch set (#8).
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
mb/google/volteer: fix incorrect fields in SPDs
According to Intel Document #616599, 1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10 columns) 2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel x16)
This change fixes those two values in the existing SPD files for Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a generic SPD).
BUG=b:152827558 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Volteer to kernel.
Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40242/8
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40242/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40242/6//COMMIT_MSG@16 PS6, Line 16: zero'd
zero’s ?
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
Patch Set 8: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40242 )
Change subject: mb/google/volteer: fix incorrect fields in SPDs ......................................................................
mb/google/volteer: fix incorrect fields in SPDs
According to Intel Document #616599, 1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10 columns) 2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel x16)
This change fixes those two values in the existing SPD files for Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a generic SPD).
BUG=b:152827558 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Volteer to kernel.
Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1 Signed-off-by: Nick Vaccaro nvaccaro@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/40242 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Caveh Jalali caveh@chromium.org --- M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex M src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex 2 files changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Caveh Jalali: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex index a94b41a..94f258e 100644 --- a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex +++ b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex @@ -1,4 +1,4 @@ -23 11 11 0E 15 19 95 08 00 00 00 00 02 21 00 00 +23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex index 7ef8220..90202f9 100644 --- a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex +++ b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex @@ -1,4 +1,4 @@ -23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 +23 11 11 0E 15 21 B5 08 00 00 00 00 0A 01 00 00 48 00 04 00 92 54 05 00 87 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Caveh Jalali (Code Review) -
Furquan Shaikh (Code Review)
-
Nick Vaccaro (Code Review)
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Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)