Change in ...coreboot[master]: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK

[Arthur Heymans (Code Review)]

Hello Patrick Rudolph, Julius Werner, Patrick Rudolph, Matt DeVillier, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/26859

to look at the new patch set (#51).

Change subject: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................

cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK

This puts the cache as ram in the bootblock.
Before setting up cache as ram the microcode updates are applied.

This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.

This adds a linker symbol _car_bist_result to easily share to bist
result between stages.

Tested on Google peppy (Acer C720).

Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, hence BOOTBLOCK_CONSOLE is not yet enabled by
default.

Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/haswell/Kconfig
M src/cpu/intel/haswell/Makefile.inc
M src/cpu/intel/haswell/bootblock.c
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/haswell/Makefile.inc
M src/northbridge/intel/haswell/bootblock.c
M src/southbridge/intel/lynxpoint/Kconfig
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/bootblock.c
M src/southbridge/intel/lynxpoint/early_pch.c
11 files changed, 33 insertions(+), 77 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/26859/51