Attention is currently required from: Hung-Te Lin, Paul Menzel, Rex-BC Chen, Yu-Ping Wu. Xixi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61294 )
Change subject: soc/mediatek: Save dramc_param header to mrc_cache ......................................................................
Patch Set 2:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61294/comment/2306f7e3_c2fc777a PS1, Line 13: TEST=fast calibration pass
On which devices?
Done
File src/soc/mediatek/common/memory.c:
https://review.coreboot.org/c/coreboot/+/61294/comment/765e944b_0abf8709 PS1, Line 181: mem_init_set_default_config
If the mrc_cache data is valid, then the whole dparam will be overwritten, which makes this call use […]
Right, remove it.
https://review.coreboot.org/c/coreboot/+/61294/comment/04890a40_544c74f0 PS1, Line 185: mrc_cache_size
Could be moved to the previous line.
Done
https://review.coreboot.org/c/coreboot/+/61294/comment/fa5e7ccb_a45a8104 PS1, Line 197: &dparam->dramc_datas
dparam
Done
https://review.coreboot.org/c/coreboot/+/61294/comment/275f8a98_439306b0 PS1, Line 201: mrc_cache_size
Same.
Done
https://review.coreboot.org/c/coreboot/+/61294/comment/f4bfe906_1d9d902f PS1, Line 214: mem_init_set_default_config(dparam, dram_info);
BTW, why do we need to set […]
On early platform, eg: 8192, the dram type is passed by coreboot instead of blob itself. Dram type is decided by HW trap(eg: GPIO mux, 001 -> discrete, 002: emcp..), not SW. So need to pass them to blob.
On 8186, only LP4X discrete is supported, so ddr_type can ignore. I think this should confirm with HW PCB member again that: no different HW trap? Is it?
"ddr_geometry" is the same, on early platform, dram size adaptive(eg: detect 4GB is rank0 4GB or rank0 2GB + rank1 2GB) may be not ready. Later, the feature is completed ready, so this can ignore by these projects.
I'd prefer to keep this function call, because maybe later platform supports more than one dram type.