[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Update UFS disable sequence

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik.

Hello Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86170?usp=email

to look at the new patch set (#2).

Change subject: soc/intel/alderlake/romstage: Update UFS disable sequence
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soc/intel/alderlake/romstage: Update UFS disable sequence

Currently after UFS is disabled, if the device is coming out of S5 sleep
state then a warm reset is triggered such that PMC samples the UFS
function disable bit and disables the UFS controller accordingly.
Sometimes during the boot flow, an additional kind of reset gets
triggered - Power cycle Reset through CMoff. Hence initiate a warm reset
when the host comes out of S5 sleep state or Power cycle Reset through
CMoff.

BUG=b:391449110
TEST=Build Brox BIOS image and boot to OS. Ensure that when the device
switches from normal mode to developer mode an extra warm reset is
triggered such that the UFS controller is disabled.

Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/soc/intel/alderlake/romstage/romstage.c
1 file changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/86170/2