Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33418 )
Change subject: soc/intel/fsp_broadwell_de: Implement SystemAgent TSEG functions ......................................................................
soc/intel/fsp_broadwell_de: Implement SystemAgent TSEG functions
Implement sa_get_tseg_base and sa_get_tseg_size.
Used by Intel TXT and the new SMM API.
Tested on OCP/Wedge100S.
Change-Id: I22123cbf8d65b25a77fbf72ae8411b23b10c13b4 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33418 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h M src/soc/intel/fsp_broadwell_de/memmap.c 2 files changed, 33 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h index edfeafc..4167895 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h @@ -18,6 +18,9 @@ #ifndef _SOC_BROADWELL_DE_H_ #define _SOC_BROADWELL_DE_H_
+uintptr_t sa_get_tseg_base(void); +size_t sa_get_tseg_size(void); + #define VTBAR_OFFSET 0x180 #define VTBAR_MASK 0xffffe000 #define VTBAR_ENABLED 0x01 diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c index 7510094..36f400c 100644 --- a/src/soc/intel/fsp_broadwell_de/memmap.c +++ b/src/soc/intel/fsp_broadwell_de/memmap.c @@ -14,10 +14,40 @@ * GNU General Public License for more details. */
+#define __SIMPLE_DEVICE__ + #include <cbmem.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <soc/broadwell_de.h> +#include <soc/pci_devs.h> +#include <device/pci_ops.h>
void *cbmem_top(void) { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } + +/* + * Get TSEG base. + */ +uintptr_t sa_get_tseg_base(void) +{ + const pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC); + + /* All regions concerned for have 1 MiB alignment. */ + return ALIGN_DOWN(pci_read_config32(dev, TSEG_BASE), 1 * MiB); +} + +size_t sa_get_tseg_size(void) +{ + const pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC); + + /* All regions concerned for have 1 MiB alignment. */ + size_t ret = ALIGN_DOWN(pci_read_config32(dev, TSEG_LIMIT), 1 * MiB); + + /* Lower 20bit of TSEG_LIMIT are don't care, need to add 1MiB */ + ret += 1 * MiB; + + /* Subtract base to get the size */ + return ret - sa_get_tseg_base(); +}