Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28767 )
Change subject: amd/stoneyridge: Load AOAC and USB gnvs values ......................................................................
Patch Set 1:
(1 comment)
Sorry, 0x71 is the state
Sorry, 0x5F is the state Sorry, 0x77 is the state
I'm not certain what you're saying. Do you think these are OK as-is?
https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge.... File src/soc/amd/stoneyridge/southbridge.c:
https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge.... PS1, Line 914: 1;
Can you be sure it'll be enabled? ESPI is not the same as SPI. […]
No, not certain. This will eventually be used for SD. I'll update the source.
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Marshall Dawson (Code Review)