Change in coreboot[master]: soc/intel/alderlake: provide a list of D-states to enter LPM

[Tarun Tuli (Code Review)]

Attention is currently required from: Lance Zhao, Subrata Banik, Tim Wawrzynczak.
Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Tim Wawrzynczak,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63969

to look at the new patch set (#7).

Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
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soc/intel/alderlake: provide a list of D-states to enter LPM

Implement sub-function 1 (Get Device Constraints)
of the Low Power S0 Idle Device-Specific Method (_DSM).
That provides a way in which to describe various devices required
D-states to enter LPM (S0ix).  This information can be used to help in
diagnostics and understanding of S0ix entry failure.

This implementation adds support for ADL.  Other SoC's could be
ported to included as well.  If they aren't, they will default to
the existing behavior of a single hardcoded device to ensure compatibility
with Windows.

TEST=Built and tested on brya by verifying SSDT contents

Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437
Signed-off-by: Tarun Tuli 
---
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/alderlake/chip.c
M src/soc/intel/common/block/acpi/pep.c
M src/soc/intel/common/block/uart/uart.c
6 files changed, 418 insertions(+), 26 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63969/7