Attention is currently required from: Furquan Shaikh, Aaron Durbin. Hello Furquan Shaikh, Aaron Durbin,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/49332
to review the following change.
Change subject: memlayout: Store region sizes as separate symbols ......................................................................
memlayout: Store region sizes as separate symbols
This patch changes the memlayout macro infrastructure so that the size of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx) is stored in a separate _xxx_size symbol. This has the advantage that region sizes can be used inside static initializers, and also saves an extra subtraction at runtime. Since linker symbols can only be treated as addresses (not as raw integers) by C, retain the REGION_SIZE() accessor macro to hide the necessary typecast.
Signed-off-by: Julius Werner jwerner@chromium.org Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373 --- M src/arch/x86/c_start.S M src/arch/x86/car.ld M src/include/memlayout.h M src/include/symbols.h M src/lib/program.ld M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/rockchip/rk3288/memlayout.ld M src/soc/rockchip/rk3399/memlayout.ld M src/soc/sifive/fu540/memlayout.ld 15 files changed, 71 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/49332/1
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 8bebf87..19532d8 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -8,6 +8,7 @@ .section .bss, "aw", @nobits .global _stack .global _estack +.global _stack_size
/* Stack alignment is not enforced with rmodule loader, reserve one * extra CPU such that alignment can be enforced on entry. */ @@ -15,6 +16,7 @@ _stack: .space (CONFIG_MAX_CPUS+1)*CONFIG_STACK_SIZE _estack: +.set _stack_size, _estack - _stack #if CONFIG(COOP_MULTITASKING) .global thread_stacks thread_stacks: diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 9f8c2ad..efc002b 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -13,6 +13,7 @@ _pagetables = . ; . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; _epagetables = . ; + RECORD_SIZE(pagetables) #endif #if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) /* Vboot work buffer only needs to be available when verified boot @@ -30,6 +31,7 @@ _car_stack = .; . += CONFIG_DCACHE_BSP_STACK_SIZE; _ecar_stack = .; + RECORD_SIZE(car_stack) /* The pre-ram cbmem console as well as the timestamp region are fixed * in size. Therefore place them above the car global section so that * multiple stages (romstage and verstage) have a consistent @@ -44,6 +46,7 @@ _pdpt = .; . += 32; _epdpt = .; + RECORD_SIZE(pdpt) #endif
TIMESTAMP(., 0x200) @@ -59,6 +62,7 @@ /* Reserve sizeof(struct ehci_dbg_info). */ . += 80; _ecar_ehci_dbg_info = .; + RECORD_SIZE(car_ehci_dbg_info)
/* _bss and _ebss provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram @@ -74,6 +78,7 @@ *(.sbss.*) . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; + RECORD_SIZE(bss)
#if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE) _shadow_size = (_ebss - _car_region_start) >> 3; diff --git a/src/include/memlayout.h b/src/include/memlayout.h index bf830b7..7e90da6 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -33,22 +33,33 @@ SET_COUNTER(name, addr) \ _##name = .;
+#define RECORD_SIZE(name) \ + _##name##_size = _e##name - _##name; + #define REGION(name, addr, size, expected_align) \ SYMBOL(name, addr) \ _ = ASSERT(. == ALIGN(expected_align), \ STR(name must be aligned to expected_align!)); \ - SYMBOL(e##name, addr + size) + SYMBOL(e##name, addr + size) \ + RECORD_SIZE(name)
#define ALIAS_REGION(name, alias) \ _##alias = _##name; \ - _e##alias = _e##name; + _e##alias = _e##name; \ + RECORD_SIZE(alias) + +#define REGION_START(name, addr) SYMBOL(name, addr) + +#define REGION_END(name, addr) \ + SYMBOL(e##name, addr) \ + RECORD_SIZE(name)
/* Declare according to SRAM/DRAM ranges in SoC hardware-defined address map. */ -#define SRAM_START(addr) SYMBOL(sram, addr) +#define SRAM_START(addr) REGION_START(sram, addr)
-#define SRAM_END(addr) SYMBOL(esram, addr) +#define SRAM_END(addr) REGION_END(sram, addr)
-#define DRAM_START(addr) SYMBOL(dram, addr) +#define DRAM_START(addr) REGION_START(dram, addr)
#define TIMESTAMP(addr, size) \ REGION(timestamp, addr, size, 8) \ @@ -113,6 +124,7 @@ #define BOOTBLOCK(addr, sz) \ SYMBOL(bootblock, addr) \ _ebootblock = _bootblock + sz; \ + RECORD_SIZE(bootblock) \ _ = ASSERT(_eprogram - _program <= sz, \ STR(Bootblock exceeded its allotted size! (sz))); \ INCLUDE "bootblock/lib/program.ld" @@ -125,6 +137,7 @@ #define ROMSTAGE(addr, sz) \ SYMBOL(romstage, addr) \ _eromstage = _romstage + sz; \ + RECORD_SIZE(romstage) \ _ = ASSERT(_eprogram - _program <= sz, \ STR(Romstage exceeded its allotted size! (sz))); \ INCLUDE "romstage/lib/program.ld" @@ -137,6 +150,7 @@ #define RAMSTAGE(addr, sz) \ SYMBOL(ramstage, addr) \ _eramstage = _ramstage + sz; \ + RECORD_SIZE(ramstage) \ _ = ASSERT(_eprogram - _program <= sz, \ STR(Ramstage exceeded its allotted size! (sz))); \ INCLUDE "ramstage/lib/program.ld" @@ -161,6 +175,7 @@ #define VERSTAGE(addr, sz) \ SYMBOL(verstage, addr) \ _everstage = _verstage + sz; \ + RECORD_SIZE(verstage) \ _ = ASSERT(_eprogram - _program <= sz, \ STR(Verstage exceeded its allotted size! (sz))); \ INCLUDE "verstage/lib/program.ld" @@ -180,6 +195,7 @@ #define POSTCAR(addr, sz) \ SYMBOL(postcar, addr) \ _epostcar = _postcar + sz; \ + RECORD_SIZE(postcar) \ _ = ASSERT(_eprogram - _program <= sz, \ STR(Aftercar exceeded its allotted size! (sz))); \ INCLUDE "postcar/lib/program.ld" diff --git a/src/include/symbols.h b/src/include/symbols.h index 6fe24f5..fe449d9 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -7,11 +7,12 @@
extern u8 _dram[];
-#define REGION_SIZE(name) (_e##name - _##name) +#define REGION_SIZE(name) ((size_t)_##name##_size)
#define DECLARE_REGION(name) \ extern u8 _##name[]; \ - extern u8 _e##name[]; + extern u8 _e##name[]; \ + extern u8 _##name##_size[];
/* * Regions can be declared optional if not all configurations provide them in @@ -23,7 +24,8 @@ */ #define DECLARE_OPTIONAL_REGION(name) \ __weak extern u8 _##name[]; \ - __weak extern u8 _e##name[]; + __weak extern u8 _e##name[]; \ + __weak extern u8 _##name##_size[];
DECLARE_REGION(sram) DECLARE_OPTIONAL_REGION(timestamp) diff --git a/src/lib/program.ld b/src/lib/program.ld index 3eebd6c..381c0d6 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -27,22 +27,26 @@ _cbmem_init_hooks = .; KEEP(*(.rodata.cbmem_init_hooks)); _ecbmem_init_hooks = .; + RECORD_SIZE(cbmem_init_hooks) #endif
. = ALIGN(ARCH_POINTER_ALIGN_SIZE); _rsbe_init_begin = .; KEEP(*(.rsbe_init)); _ersbe_init_begin = .; + RECORD_SIZE(rsbe_init_begin)
#if ENV_RAMSTAGE . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _pci_drivers = .; KEEP(*(.rodata.pci_driver)); _epci_drivers = .; + RECORD_SIZE(pci_drivers) . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _cpu_drivers = .; KEEP(*(.rodata.cpu_driver)); _ecpu_drivers = .; + RECORD_SIZE(cpu_drivers) #endif
. = ALIGN(ARCH_POINTER_ALIGN_SIZE); @@ -50,6 +54,7 @@ *(.rodata.*); . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _etext = .; + RECORD_SIZE(text) } : to_load
#if ENV_RAMSTAGE && (CONFIG(COVERAGE) || CONFIG(ASAN_IN_RAMSTAGE)) @@ -80,6 +85,7 @@ _rmodule_params = .; KEEP(*(.module_parameters)); _ermodule_params = .; + RECORD_SIZE(rmodule_params) #endif
*(.data); @@ -90,6 +96,7 @@ #if ENV_ROMSTAGE_OR_BEFORE PROVIDE(_preram_cbmem_console = .); PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); + PROVIDE(_preram_cbmem_console_size = 0); #elif ENV_RAMSTAGE . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bs_init_begin = .; @@ -97,10 +104,12 @@ LONG(0); LONG(0); _ebs_init_begin = .; + RECORD_SIZE(bs_init_begin) #endif
. = ALIGN(ARCH_POINTER_ALIGN_SIZE); _edata = .; + RECORD_SIZE(data) } #endif
@@ -114,6 +123,7 @@ *(.sbss.*) . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; + RECORD_SIZE(bss) } #endif
@@ -124,6 +134,7 @@ . += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE); . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _eheap = .; + RECORD_SIZE(heap) } #endif
@@ -133,6 +144,7 @@ #endif
_eprogram = .; +RECORD_SIZE(program)
/* Discard the sections we don't need/want */
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index 352472e..d2708b9 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -4,11 +4,11 @@ #include <arch/header.ld> #include <soc/psp_transfer.h>
-#define EARLY_RESERVED_DRAM_START(addr) SYMBOL(early_reserved_dram, addr) -#define EARLY_RESERVED_DRAM_END(addr) SYMBOL(eearly_reserved_dram, addr) +#define EARLY_RESERVED_DRAM_START(addr) REGION_START(early_reserved_dram, addr) +#define EARLY_RESERVED_DRAM_END(addr) REGION_END(eearly_reserved_dram, addr)
-#define PSP_SHAREDMEM_DRAM_START(addr) SYMBOL(psp_sharedmem_dram, addr) -#define PSP_SHAREDMEM_DRAM_END(addr) SYMBOL(epsp_sharedmem_dram, addr) +#define PSP_SHAREDMEM_DRAM_START(addr) REGION_START(psp_sharedmem_dram, addr) +#define PSP_SHAREDMEM_DRAM_END(addr) REGION_END(epsp_sharedmem_dram, addr)
BOOTBLOCK_END = CONFIG_ROMSTAGE_ADDR; BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE; diff --git a/src/soc/mediatek/mt8173/memlayout.ld b/src/soc/mediatek/mt8173/memlayout.ld index d9a6d83..092cfdf 100644 --- a/src/soc/mediatek/mt8173/memlayout.ld +++ b/src/soc/mediatek/mt8173/memlayout.ld @@ -9,8 +9,8 @@ * It will be returned before starting the ramstage. * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. */ -#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) -#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) +#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) +#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
#define DRAM_DMA(addr, size) \ REGION(dram_dma, addr, size, 4K) \ diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld index a549274..0acd174 100644 --- a/src/soc/mediatek/mt8183/memlayout.ld +++ b/src/soc/mediatek/mt8183/memlayout.ld @@ -9,8 +9,8 @@ * It will be returned before starting the ramstage. * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. */ -#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) -#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) +#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) +#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) #define DRAM_INIT_CODE(addr, size) \ REGION(dram_init_code, addr, size, 4)
diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index 2a21dd6..06852d1 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -9,8 +9,8 @@ * It will be returned before starting the ramstage. * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. */ -#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) -#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) +#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) +#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) #define DRAM_INIT_CODE(addr, size) \ REGION(dram_init_code, addr, size, 4)
diff --git a/src/soc/qualcomm/ipq40xx/memlayout.ld b/src/soc/qualcomm/ipq40xx/memlayout.ld index 4c54294..e630e74 100644 --- a/src/soc/qualcomm/ipq40xx/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/memlayout.ld @@ -4,9 +4,6 @@
#include <arch/header.ld>
-#define REGION_START(name, addr) SYMBOL(name, addr) -#define REGION_END(name, addr) SYMBOL(e##name, addr) - SECTIONS { REGION(oc_imem, 0x08600000, 32K, 0) diff --git a/src/soc/qualcomm/qcs405/memlayout.ld b/src/soc/qualcomm/qcs405/memlayout.ld index a282512..348fb43 100644 --- a/src/soc/qualcomm/qcs405/memlayout.ld +++ b/src/soc/qualcomm/qcs405/memlayout.ld @@ -4,12 +4,12 @@ #include <arch/header.ld>
/* SYSTEM_IMEM : 0x8600000 - 0x8607FFF */ -#define SSRAM_START(addr) SYMBOL(ssram, addr) -#define SSRAM_END(addr) SYMBOL(essram, addr) +#define SSRAM_START(addr) REGION_START(ssram, addr) +#define SSRAM_END(addr) REGION_END(ssram, addr)
/* BOOT_IMEM : 0x8C00000 - 0x8D80000 */ -#define BSRAM_START(addr) SYMBOL(bsram, addr) -#define BSRAM_END(addr) SYMBOL(ebsram, addr) +#define BSRAM_START(addr) REGION_START(bsram, addr) +#define BSRAM_END(addr) REGION_END(bsram, addr)
SECTIONS { diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index ca9c993..1b9044f 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -4,16 +4,16 @@ #include <arch/header.ld>
/* SYSTEM_IMEM : 0x14680000 - 0x146AE000 */ -#define SSRAM_START(addr) SYMBOL(ssram, addr) -#define SSRAM_END(addr) SYMBOL(essram, addr) +#define SSRAM_START(addr) REGION_START(ssram, addr) +#define SSRAM_END(addr) REGION_END(ssram, addr)
/* BOOT_IMEM : 0x14800000 - 0x14980000 */ -#define BSRAM_START(addr) SYMBOL(bsram, addr) -#define BSRAM_END(addr) SYMBOL(ebsram, addr) +#define BSRAM_START(addr) REGION_START(bsram, addr) +#define BSRAM_END(addr) REGION_END(bsram, addr)
/* AOP : 0x0B000000 - 0x0B100000 */ -#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) -#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) +#define AOPSRAM_START(addr) REGION_START(aopsram, addr) +#define AOPSRAM_END(addr) REGION_END(aopsram, addr)
SECTIONS { diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld index 4ef0163..4a0acbc 100644 --- a/src/soc/rockchip/rk3288/memlayout.ld +++ b/src/soc/rockchip/rk3288/memlayout.ld @@ -28,8 +28,8 @@
/* 4K of special SRAM in PMU power domain. * Careful: only supports 32-bit wide write accesses! */ - SYMBOL(pmu_sram, 0xFF720000) + REGION_START(pmu_sram, 0xFF720000) TTB_SUBTABLES(0xFF720800, 1K) WATCHDOG_TOMBSTONE(0xFF720FFC, 4) - SYMBOL(epmu_sram, 0xFF721000) + REGION_END(epmu_sram, 0xFF721000) } diff --git a/src/soc/rockchip/rk3399/memlayout.ld b/src/soc/rockchip/rk3399/memlayout.ld index aa925a2..5f76928 100644 --- a/src/soc/rockchip/rk3399/memlayout.ld +++ b/src/soc/rockchip/rk3399/memlayout.ld @@ -12,9 +12,9 @@ DMA_COHERENT(0x10000000, 2M)
/* 8K of special SRAM in PMU power domain. */ - SYMBOL(pmu_sram, 0xFF3B0000) + REGION_START(pmu_sram, 0xFF3B0000) WATCHDOG_TOMBSTONE(0xFF3B1FFC, 4) - SYMBOL(epmu_sram, 0xFF3B2000) + REGION_END(epmu_sram, 0xFF3B2000)
SRAM_START(0xFF8C0000) #if ENV_RAMSTAGE diff --git a/src/soc/sifive/fu540/memlayout.ld b/src/soc/sifive/fu540/memlayout.ld index b365b96..73faa4b 100644 --- a/src/soc/sifive/fu540/memlayout.ld +++ b/src/soc/sifive/fu540/memlayout.ld @@ -5,8 +5,8 @@
#include <arch/header.ld>
-#define L2LIM_START(addr) SYMBOL(l2lim, addr) -#define L2LIM_END(addr) SYMBOL(el2lim, addr) +#define L2LIM_START(addr) REGION_START(l2lim, addr) +#define L2LIM_END(addr) REGION_END(l2lim, addr)
SECTIONS {
-
Julius Werner (Code Review)