Change in coreboot[master]: sandybridge/raminit_common.c: fix printram statement

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28117 )

Change subject: sandybridge/raminit_common.c: fix printram statement
......................................................................

sandybridge/raminit_common.c: fix printram statement

Change-Id: Iddea8cc71dc1fb33d46b22dd19e39bf1c1257555
Signed-off-by: Iru Cai 
Reviewed-on: https://review.coreboot.org/28117
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 8 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved

diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index d806066..a90b055 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -195,7 +195,7 @@
 static void dram_odt_stretch(ramctr_timing *ctrl, int channel)
 {
    struct cpuid_result cpures;
-	u32 cpu, stretch;
+	u32 addr, cpu, stretch;

stretch = ctrl->ref_card_offset[channel];
    /* ODT stretch: Delay ODT signal by stretch value.
@@ -205,14 +205,17 @@
    if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) {
    	if (stretch == 2)
    		stretch = 3;
-		MCHBAR32_AND_OR(0x401c + 0x400 * channel, 0xffffc3ff,
+		addr = 0x401c + 0x400 * channel;
+		MCHBAR32_AND_OR(addr, 0xffffc3ff,
    		(stretch << 12) | (stretch << 10));
-		printram("OTHP Workaround [%x] = %x\n", addr, reg);
+		printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr,
+			MCHBAR32(addr));
    } else {
    	// OTHP
-		MCHBAR32_AND_OR(0x400c + 0x400 * channel, 0xfff0ffff,
+		addr = 0x400c + 0x400 * channel;
+		MCHBAR32_AND_OR(addr, 0xfff0ffff,
    		(stretch << 16) | (stretch << 18));
-		printram("OTHP [%x] = %x\n", addr, reg);
+		printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr));
    }
 }