[S] Change in coreboot[master]: soc/amd/sata.c: Hook up directly in devicetree

[Arthur Heymans (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held.

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68142 )

Change subject: soc/amd/sata.c: Hook up directly in devicetree
......................................................................

soc/amd/sata.c: Hook up directly in devicetree

Change-Id: If7f0a9638151cf981d891464a2c3a0ec5fc9c780
Signed-off-by: Arthur Heymans 
---
M src/soc/amd/cezanne/chipset.cb
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/picasso/chipset.cb
3 files changed, 14 insertions(+), 21 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/68142/1

diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb
index fa42e8a..d975fcf 100644
--- a/src/soc/amd/cezanne/chipset.cb
+++ b/src/soc/amd/cezanne/chipset.cb
@@ -81,8 +81,8 @@
    		device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
    	end
    	device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
-			device pci 0.0 alias sata_0 off end # first SATA controller; AHCI Mode
-			device pci 0.1 alias sata_1 off end # second SATA Controller; SATA Raid/AHCI Mode
+			device pci 0.0 alias sata_0 off ops amd_sata_ops end # first SATA controller; AHCI Mode
+			device pci 0.1 alias sata_1 off ops amd_sata_ops end # second SATA Controller; SATA Raid/AHCI Mode
    		device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0)
    		device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1)
    	end
diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c
index 19a7d3e..6a27168 100644
--- a/src/soc/amd/common/block/sata/sata.c
+++ b/src/soc/amd/common/block/sata/sata.c
@@ -3,7 +3,6 @@
 #include <acpi/acpigen.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
 #include <amdblocks/sata.h>

static const char *sata_acpi_name(const struct device *dev)
@@ -11,7 +10,7 @@
    return "STCR";
 }

-static struct device_operations sata_ops = {
+struct device_operations amd_sata_ops = {
    .read_resources		= pci_dev_read_resources,
    .set_resources		= pci_dev_set_resources,
    .enable_resources	= pci_dev_enable_resources,
@@ -20,19 +19,3 @@
    .acpi_name		= sata_acpi_name,
    .acpi_fill_ssdt		= acpi_device_write_pci_dev,
 };
-
-static const unsigned short pci_device_ids[] = {
-	PCI_DID_AMD_CZ_SATA,
-	PCI_DID_AMD_CZ_SATA_AHCI,
-	PCI_DID_AMD_FAM17H_SATA_AHCI_VER0,
-	PCI_DID_AMD_FAM17H_SATA_AHCI_VER1,
-	PCI_DID_AMD_FAM17H_SATA_AHCI_RAID_VER0,
-	PCI_DID_AMD_FAM17H_SATA_AHCI_RAID_VER1,
-	0
-};
-
-static const struct pci_driver sata0_driver __pci_driver = {
-	.ops			= &sata_ops,
-	.vendor			= PCI_VID_AMD,
-	.devices		= pci_device_ids,
-};
diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb
index 1fee7f8..6fcfd41 100644
--- a/src/soc/amd/picasso/chipset.cb
+++ b/src/soc/amd/picasso/chipset.cb
@@ -28,7 +28,7 @@
    		device pci 0.7 alias mp2 off end # sensor fusion hub (MP2)
    	end
    	device pci 08.2 alias internal_bridge_b off # internal bridge to bus B
-			device pci 0.0 alias sata off end
+			device pci 0.0 alias sata off ops amd_sata_ops end
    		device pci 0.1 alias xgbe_0 off end
    		device pci 0.2 alias xgbe_1 off end
    	end