Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47188 )
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
mb/purism/librem_mini: Reorganize devicetree
Move registers under devices to which they belong.
Change-Id: I61ca7c1db02646252d7421f8b79dfc8a40b2bdb5 Signed-off-by: Matt DeVillier matt.devillier@puri.sm --- M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 1 file changed, 27 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47188/1
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index ae19b04..c69f3f6 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -18,30 +18,6 @@ register "SaGv" = "SaGv_Enabled"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # SATA - register "SataMode" = "Sata_AHCI" - register "SataPortsEnable[0]" = "1" # 2.5" - register "SataPortsEnable[2]" = "1" # m.2 - - # Audio - register "PchHdaAudioLinkHda" = "1" - - # USB2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper - register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth - register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower - - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper
# All SRCCLKREQ pins mapped directly register "PcieClkSrcClkReq[0]" = "0" @@ -59,20 +35,8 @@ register "PcieClkSrcUsage[4]" = "0x80" register "PcieClkSrcUsage[5]" = "0x80"
- # PCI Express Root Port #8 x1, Clock 2 (WLAN) - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - - # PCI Express Root Port #10 x1, Clock 3 (LAN) - register "PcieRpEnable[9]" = "1" - - # PCI Express Root port #13 x4, Clock 1 (NVMe) - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - # Misc register "AcousticNoiseMitigation" = "1" - register "satapwroptimize" = "1"
# Power register "PchPmSlpS3MinAssert" = "3" # 50ms @@ -198,6 +162,19 @@ end end end + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth + register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper end device pci 14.1 off end # USB xDCI (OTG) device pci 15.0 off end # I2C #0 @@ -210,7 +187,12 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA + device pci 17.0 on # SATA + register "SataMode" = "Sata_AHCI" + register "SataPortsEnable[0]" = "1" # 2.5" + register "SataPortsEnable[2]" = "1" # m.2 + register "satapwroptimize" = "1" + end device pci 19.0 off end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 off end # UART #2 @@ -224,15 +206,20 @@ device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on # PCI Express Port 8 (WLAN) register "PcieRpSlotImplemented[7]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" end device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 on # PCI Express Port 10 (LAN) register "PcieRpSlotImplemented[9]" = "1" + register "PcieRpEnable[9]" = "1" end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on # PCI Express Port 13 (NVMe) register "PcieRpSlotImplemented[12]" = "1" + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" end device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 @@ -244,7 +231,9 @@ device pci 1f.0 on end # LPC Bridge device pci 1f.1 off end # P2SB device pci 1f.2 off end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkHda" = "1" + end device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47188 )
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
Patch Set 1: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47188 )
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... File src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... PS1, Line 22: # All SRCCLKREQ pins mapped directly : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : : # Set all SRCCLKREQ pins as free-use : register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80" what about these?
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47188 )
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... File src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... PS1, Line 22: # All SRCCLKREQ pins mapped directly : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : : # Set all SRCCLKREQ pins as free-use : register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80"
what about these?
where should they go, given they are not assigned to a particular root port?
Hello build bot (Jenkins), Paul Menzel, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47188
to look at the new patch set (#2).
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
mb/purism/librem_mini: Reorganize devicetree
Move registers under devices to which they belong.
Change-Id: I61ca7c1db02646252d7421f8b79dfc8a40b2bdb5 Signed-off-by: Matt DeVillier matt.devillier@puri.sm --- M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 1 file changed, 27 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47188/2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47188 )
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... File src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... PS1, Line 22: # All SRCCLKREQ pins mapped directly : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : : # Set all SRCCLKREQ pins as free-use : register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80"
where should they go, given they are not assigned to a particular root port?
are they in use at all? connected to anything?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47188 )
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... File src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... PS1, Line 22: # All SRCCLKREQ pins mapped directly : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : : # Set all SRCCLKREQ pins as free-use : register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80"
are they in use at all? connected to anything?
We had some problems with PCIe clocks not working as intended, which is why these settings are not optimal (but they work, which is what matters). Currently, all clock sources are configured as free-running (not tied to any particular PCIe root port). Most boards don't cross CLKREQ# and CLKSRC, which is why they're directly-mapped.
I figured out how the ClkSrcUsage settings work, and I'll revise these settings later.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47188 )
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... File src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... PS1, Line 22: # All SRCCLKREQ pins mapped directly : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : : # Set all SRCCLKREQ pins as free-use : register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80"
We had some problems with PCIe clocks not working as intended, which is why these settings are not o […]
Doesn't answer the question :P > are they in use at all? connected to anything?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47188 )
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
Patch Set 2: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47188 )
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... File src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... PS1, Line 22: # All SRCCLKREQ pins mapped directly : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : : # Set all SRCCLKREQ pins as free-use : register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80"
Doesn't answer the question :P > are they in use at all? connected to anything?
Answer: yes, they are.
Right settings should be:
# All SRCCLKREQ pins mapped directly register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcClkReq[3]" = "3"
# Set all SRCCLKREQ pins as free-use register "PcieClkSrcUsage[0]" = "0xff" register "PcieClkSrcUsage[1]" = "12" # NVME register "PcieClkSrcUsage[2]" = "7" # WIFI register "PcieClkSrcUsage[3]" = "9" # LAN register "PcieClkSrcUsage[4]" = "0xff" register "PcieClkSrcUsage[5]" = "0xff"
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47188 )
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... File src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... PS1, Line 22: # All SRCCLKREQ pins mapped directly : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : : # Set all SRCCLKREQ pins as free-use : register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80"
Answer: yes, they are. […]
woops, shouldn't block. this is a different change
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47188 )
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
mb/purism/librem_mini: Reorganize devicetree
Move registers under devices to which they belong.
Change-Id: I61ca7c1db02646252d7421f8b79dfc8a40b2bdb5 Signed-off-by: Matt DeVillier matt.devillier@puri.sm Reviewed-on: https://review.coreboot.org/c/coreboot/+/47188 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 1 file changed, 27 insertions(+), 38 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index ae19b04..c69f3f6 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -18,30 +18,6 @@ register "SaGv" = "SaGv_Enabled"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # SATA - register "SataMode" = "Sata_AHCI" - register "SataPortsEnable[0]" = "1" # 2.5" - register "SataPortsEnable[2]" = "1" # m.2 - - # Audio - register "PchHdaAudioLinkHda" = "1" - - # USB2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper - register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth - register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower - - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper
# All SRCCLKREQ pins mapped directly register "PcieClkSrcClkReq[0]" = "0" @@ -59,20 +35,8 @@ register "PcieClkSrcUsage[4]" = "0x80" register "PcieClkSrcUsage[5]" = "0x80"
- # PCI Express Root Port #8 x1, Clock 2 (WLAN) - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - - # PCI Express Root Port #10 x1, Clock 3 (LAN) - register "PcieRpEnable[9]" = "1" - - # PCI Express Root port #13 x4, Clock 1 (NVMe) - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - # Misc register "AcousticNoiseMitigation" = "1" - register "satapwroptimize" = "1"
# Power register "PchPmSlpS3MinAssert" = "3" # 50ms @@ -198,6 +162,19 @@ end end end + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth + register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper end device pci 14.1 off end # USB xDCI (OTG) device pci 15.0 off end # I2C #0 @@ -210,7 +187,12 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA + device pci 17.0 on # SATA + register "SataMode" = "Sata_AHCI" + register "SataPortsEnable[0]" = "1" # 2.5" + register "SataPortsEnable[2]" = "1" # m.2 + register "satapwroptimize" = "1" + end device pci 19.0 off end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 off end # UART #2 @@ -224,15 +206,20 @@ device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on # PCI Express Port 8 (WLAN) register "PcieRpSlotImplemented[7]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" end device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 on # PCI Express Port 10 (LAN) register "PcieRpSlotImplemented[9]" = "1" + register "PcieRpEnable[9]" = "1" end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on # PCI Express Port 13 (NVMe) register "PcieRpSlotImplemented[12]" = "1" + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" end device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 @@ -244,7 +231,9 @@ device pci 1f.0 on end # LPC Bridge device pci 1f.1 off end # P2SB device pci 1f.2 off end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkHda" = "1" + end device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47188 )
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
Patch Set 4:
(6 comments)
https://review.coreboot.org/c/coreboot/+/47188/2/src/mainboard/purism/librem... File src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/47188/2/src/mainboard/purism/librem... PS2, Line 165: OC_SKIP OC0
https://review.coreboot.org/c/coreboot/+/47188/2/src/mainboard/purism/librem... PS2, Line 166: OC_SKIP OC0
https://review.coreboot.org/c/coreboot/+/47188/2/src/mainboard/purism/librem... PS2, Line 168: OC_SKIP OC1
https://review.coreboot.org/c/coreboot/+/47188/2/src/mainboard/purism/librem... PS2, Line 169: OC_SKIP OC1
https://review.coreboot.org/c/coreboot/+/47188/2/src/mainboard/purism/librem... PS2, Line 173: OC_SKIP OC0
https://review.coreboot.org/c/coreboot/+/47188/2/src/mainboard/purism/librem... PS2, Line 174: OC_SKIP OC0
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Angel Pons (Code Review) -
Matt DeVillier (Code Review)
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Michael Niewöhner (Code Review)