Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46990 )
Change subject: nb/intel/haswell: Create RMRR for iGPU ......................................................................
nb/intel/haswell: Create RMRR for iGPU
Taken from Broadwell.
Change-Id: I246fdc1473bf8949073377d03622026bd3e6aafa Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/acpi.c 1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/46990/1
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 0e7967f..f48ef61 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -63,6 +63,21 @@ acpi_dmar_drhd_fixup(tmp, current); }
+ /* Then, add RMRR entries after all DRHD entries */ + if (emit_igd) { + const unsigned long tmp = current; + + const struct device *sa_dev = pcidev_on_root(0, 0); + + /* Bit 0 is lock bit, not part of address */ + const u32 tolud = pci_read_config32(sa_dev, TOLUD) & ~1; + const u32 bgsm = pci_read_config32(sa_dev, BGSM) & ~1; + + current += acpi_create_dmar_rmrr(current, 0, bgsm, tolud - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + return current; }
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46990
to look at the new patch set (#5).
Change subject: nb/intel/haswell: Create RMRR for iGPU ......................................................................
nb/intel/haswell: Create RMRR for iGPU
Taken from Broadwell.
Change-Id: I246fdc1473bf8949073377d03622026bd3e6aafa Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/acpi.c 1 file changed, 21 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/46990/5
Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46990 )
Change subject: nb/intel/haswell: Create RMRR for iGPU ......................................................................
Patch Set 8: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46990 )
Change subject: nb/intel/haswell: Create RMRR for iGPU ......................................................................
nb/intel/haswell: Create RMRR for iGPU
Taken from Broadwell.
Change-Id: I246fdc1473bf8949073377d03622026bd3e6aafa Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46990 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/northbridge/intel/haswell/acpi.c 1 file changed, 21 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 0601100..96448f3 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -26,8 +26,13 @@ const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ - if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { + const bool emit_igd = + igfx_dev && igfx_dev->enabled && + gfxvtbar && gfxvten && + !MCHBAR32(GFXVTBAR + 4);
+ /* First, add DRHD entries */ + if (emit_igd) { const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); @@ -51,6 +56,21 @@ acpi_dmar_drhd_fixup(tmp, current); }
+ /* Then, add RMRR entries after all DRHD entries */ + if (emit_igd) { + const unsigned long tmp = current; + + const struct device *sa_dev = pcidev_on_root(0, 0); + + /* Bit 0 is lock bit, not part of address */ + const u32 tolud = pci_read_config32(sa_dev, TOLUD) & ~1; + const u32 bgsm = pci_read_config32(sa_dev, BGSM) & ~1; + + current += acpi_create_dmar_rmrr(current, 0, bgsm, tolud - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + return current; }
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46990 )
Change subject: nb/intel/haswell: Create RMRR for iGPU ......................................................................
Patch Set 9:
(1 comment)
File src/northbridge/intel/haswell/acpi.c:
https://review.coreboot.org/c/coreboot/+/46990/comment/d3f4afb9_7bfad989 PS9, Line 31: && : !MCHBAR32(GFXVTBAR + 4) NB. IIRC, this is not required anymore as the ACPI API was fixed (supports 64-bit values now).
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46990 )
Change subject: nb/intel/haswell: Create RMRR for iGPU ......................................................................
Patch Set 9:
(1 comment)
File src/northbridge/intel/haswell/acpi.c:
https://review.coreboot.org/c/coreboot/+/46990/comment/14d64284_15fe4a7d PS9, Line 31: && : !MCHBAR32(GFXVTBAR + 4)
NB. IIRC, this is not required anymore as the ACPI API was fixed (supports […]
I'll revisit once there's only one copy of this code
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Angel Pons (Code Review) -
Nico Huber (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)