Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock - coreboot-gerrit

1 Jul 2019


      Julien Viard de Galbert has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 )
Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
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Patch Set 14:
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Patch Set 14: Code-Review+1
I tend to agree that spi probably does not belong in the function name.
Right I did probably cut spi_lock_bar in two when creating the function ... that would explain the (bad) name.
It should probably be lpc_ or pch_.
Note that I no longer work at scaleway and didn't found enough free time to setup a build environment yet.
Best Regards,
Julien VdG
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Gerrit-Change-Number: 25442
Gerrit-PatchSet: 14
Gerrit-Owner: Julien Viard de Galbert coreboot-review-ju@vdg.name
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