Change in coreboot[master]: nb/intel/i945: Programm CxODT value for each channel

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 )

Change subject: nb/intel/i945: Programm CxODT value for each channel
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Patch Set 26:

(1 comment)

https://review.coreboot.org/c/coreboot/+/18548/22/src/northbridge/intel/i945... 
File src/northbridge/intel/i945/raminit.c:

https://review.coreboot.org/c/coreboot/+/18548/22/src/northbridge/intel/i945... 
PS22, Line 2473: MCHBAR32(C1ODT)
> > High-speed electrical signalling is very cursed. […]

Right, ODT is also enabled with a single DIMM.

Oh, wait, now I recall what this register is: the ODT matrix for the MCH. It's present on various other northbridges, and it's probably the same format for i915, i945, 965gm and gm45.

In any case, I have checked that, on i915:

- ODT is only programmed for DDR2.
- Both C0ODT and C1ODT are treated the same way.
- Bits [30..28] are cleared when channel A does NOT have two DIMMs installed.
- CLKCFG bit 16 indicates Mobility Option selected. If set, CxODT uses a "half" table.
- The tables are indexed using the CAS latency.
- Range [31..0]  is programmed using 0xffff00c0 as a mask.
- Range [63..32] is programmed using 0x1ffc0000 as a mask.

The i915 tables have the following values, which are likely wrong for i945.
 static const u32 odt_full[] = {
    /* [31..0], [63..32] */
    0x0000ff15, 0xe0038798, /* DDR2 CL5 */
    0x0000aa15, 0xe0028798, /* DDR2 CL4 */
    0x00005515, 0xe0018798, /* DDR2 CL3 */
 };

static const u32 odt_half[] = {
    /* [31..0], [63..32] */
    0x0000ff15, 0xe0034454, /* DDR2 CL5 */
    0x0000aa15, 0xe0024454, /* DDR2 CL4 */
    0x00005515, 0xe0014454, /* DDR2 CL3 */
 };