Change in coreboot[master]: soc/{samsung,sifive}: Fix typos

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39016 )

Change subject: soc/{samsung,sifive}: Fix typos
......................................................................

soc/{samsung,sifive}: Fix typos

Change-Id: Ib370f04a63160e2a8a1b06620e659feb45c8f552
Signed-off-by: Elyes HAOUAS 
---
M src/soc/samsung/exynos5420/spi.c
M src/soc/sifive/fu540/clock.c
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/39016/1

diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c
index a98f51d..ec90023 100644
--- a/src/soc/samsung/exynos5420/spi.c
+++ b/src/soc/samsung/exynos5420/spi.c
@@ -101,7 +101,7 @@
    // CPOL: Active high.
    clrbits32(&regs->ch_cfg, SPI_CH_CPOL_L);

-	// Clear rx and tx channel if set priveously.
+	// Clear rx and tx channel if set previously.
    clrbits32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);

setbits32(&regs->swap_cfg,
diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c
index a15e639..ad5e06b 100644
--- a/src/soc/sifive/fu540/clock.c
+++ b/src/soc/sifive/fu540/clock.c
@@ -104,7 +104,7 @@
  * Set coreclk according to the SiFive FU540-C000 Manual
  * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
  *
- * Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 Ghz is possible)
+ * Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 GHz is possible)
  *
  * Section 7.4.2 provides the necessary values:
  * For example, to setup COREPLL for 1 GHz operation, program divr = 0 (x1),

[Jacob Garber (Code Review)]

Jacob Garber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39016 )

Change subject: soc/{samsung,sifive}: Fix typos
......................................................................

Patch Set 1: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39016 )

Change subject: soc/{samsung,sifive}: Fix typos
......................................................................

soc/{samsung,sifive}: Fix typos

Change-Id: Ib370f04a63160e2a8a1b06620e659feb45c8f552
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39016
Tested-by: build bot (Jenkins) 
Reviewed-by: Jacob Garber 
---
M src/soc/samsung/exynos5420/spi.c
M src/soc/sifive/fu540/clock.c
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Jacob Garber: Looks good to me, approved

diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c
index a98f51d..ec90023 100644
--- a/src/soc/samsung/exynos5420/spi.c
+++ b/src/soc/samsung/exynos5420/spi.c
@@ -101,7 +101,7 @@
    // CPOL: Active high.
    clrbits32(&regs->ch_cfg, SPI_CH_CPOL_L);

-	// Clear rx and tx channel if set priveously.
+	// Clear rx and tx channel if set previously.
    clrbits32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);

setbits32(&regs->swap_cfg,
diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c
index a15e639..ad5e06b 100644
--- a/src/soc/sifive/fu540/clock.c
+++ b/src/soc/sifive/fu540/clock.c
@@ -104,7 +104,7 @@
  * Set coreclk according to the SiFive FU540-C000 Manual
  * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
  *
- * Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 Ghz is possible)
+ * Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 GHz is possible)
  *
  * Section 7.4.2 provides the necessary values:
  * For example, to setup COREPLL for 1 GHz operation, program divr = 0 (x1),