Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin.
Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )
Change subject: mb/asus/p8z77-v: Add support to reconfigure PCIe lanes ......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/asus/p8x7x-series/variants/p8z77-v/pcielane.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/f4164214_0da8185b?usp... : PS8, Line 131: gpio5 = 0x20;
When PCIEPCS1 == 0, PCIEX1_2 remains not working with X_QSW_SEL2,3,4 being 111 and the following l […]
Here is the big test. Can you test changing pciex16_3_bandwidth using nvramtool? It should now also attempt to change PCIEPCS1 as well.
Be ready to recover.
Changing it between Auto/x1, x2, x4 (so that the soft strap changes) should result in 1-2 power cycles, not more. If you clean the ME, these changes should only power cycle once. And if ME is intact, it should not report as disabled after strap is updated.
Check that flash contents is preserved except the strap at offset 0x124 at all times.
Check that no reflash is attempted going in and out of S3 and everything is preserved - GPIOs, straps, functionality.
Check if PCIEX1_2 works with pciex16_3_bandwidth=x1, and SATA work with _bandwidth=Auto and always_use_sata6ge=Yes.
Check console logs.
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Keith Hui (Code Review)