Change in coreboot[master]: soc/amd/cezanne/fch: add ACPI I/O port setup

[Marshall Dawson (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held.
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50270 )

Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup
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Patch Set 1: Code-Review+2

(2 comments)

File src/soc/amd/cezanne/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/50270/comment/31854bf9_d85658b8 
PS1, Line 19: 0x0400
Curious why not use CONFIG_CEZANNE_ACPI_IO_BASE.  0x400 should be fine though.

https://review.coreboot.org/c/coreboot/+/50270/comment/664ef160_31ed8c83 
PS1, Line 25: 0x10
This differs from Picasso.  Was changed in CB:44135 however I believe we stripped it from AGESA so it shouldn't be an issue.