Change in ...coreboot[master]: post_code: add post code for hardware initialization failure
Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32774 )
Change subject: post_code: add post code for hardware initialization failure ......................................................................
post_code: add post code for hardware initialization failure
Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to detect or initialize a required hardware component.
BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms
Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552 Signed-off-by: Keith Short keithshort@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M Documentation/POSTCODES M src/console/Makefile.inc M src/include/console/post_codes.h M src/soc/intel/apollolake/memmap.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/fsp_baytrail/southcluster.c M src/soc/intel/icelake/memmap.c M src/soc/intel/quark/i2c.c 12 files changed, 34 insertions(+), 13 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES index 2a8285b..a9d392a 100644 --- a/Documentation/POSTCODES +++ b/Documentation/POSTCODES @@ -20,6 +20,7 @@ 0xe1 Resource stored within CBFS is corrupt 0xe2 Vendor binary (e.g. FSP) generated a fatal error 0xe3 RAM could not be initialized +0xe4 Critical hardware component could not initialize 0xf8 Entry into elf boot 0xf3 Jumping to payload
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index d5795d7..4f0c2ef 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -9,6 +9,7 @@
smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c +smm-$(CONFIG_SMM_TSEG) += post.c
verstage-y += init.c verstage-y += printk.c diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 07927ec..ae277d8 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -349,6 +349,13 @@ #define POST_RAM_FAILURE 0xe3
/** + * \brief Hardware initialization failure + * + * Set when a required hardware component was not found or is unsupported. + */ +#define POST_HW_INIT_FAILURE 0xe4 + +/** * \brief TPM failure * * An error with the TPM, either unexepcted state or communications failure. diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 4f91b8a..6058e34 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -40,7 +40,8 @@ config = dev->chip_info;
if (!config) - die("Failed to get chip_info\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Failed to get chip_info\n");
/* FSP allocates 2x PRMRR Size Memory for alignment */ if (config->sgx_enable) diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 1c7fd7f..c43d6d8 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -120,7 +120,8 @@
pmc_base_reg = get_pmc_reg_base(); if (!pmc_base_reg) - die("Invalid PMC base address\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Invalid PMC base address\n");
pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 3512e2c..3cae54f 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -221,7 +221,8 @@
dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); if (!dev) - die("ERROR - IGD device not found!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "ERROR - IGD device not found!");
/* Read TOLUD from Host Bridge offset */ dram_base = sa_get_tolud_base(); diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 5d3b4a1..4cea21b 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -58,7 +58,8 @@ */ uintptr_t memory_base = graphics_get_bar(PCI_BASE_ADDRESS_2); if (!memory_base) - die("GMADR is not programmed!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "GMADR is not programmed!");
return memory_base; } @@ -74,7 +75,8 @@ if (!gtt_base) { gtt_base = graphics_get_bar(PCI_BASE_ADDRESS_0); if (!gtt_base) - die("GTTMMADR is not programmed!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "GTTMMADR is not programmed!"); } return gtt_base; } diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 1d7c091..24cde1b 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -36,7 +36,8 @@ pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
if (dev == PCI_DEV_INVALID) - die("PCH_DEV_P2SB not found!\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "PCH_DEV_P2SB not found!\n");
return dev; } @@ -45,7 +46,8 @@ { struct device *dev = PCH_DEV_P2SB; if (!dev) - die("PCH_DEV_P2SB not found!\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "PCH_DEV_P2SB not found!\n");
return dev; } @@ -99,7 +101,8 @@
if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) - die("Unable to unhide PCH_DEV_P2SB device !\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to unhide PCH_DEV_P2SB device !\n"); }
void p2sb_hide(void) @@ -108,7 +111,8 @@
if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != 0xFFFF) - die("Unable to hide PCH_DEV_P2SB device !\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to hide PCH_DEV_P2SB device !\n"); }
static void p2sb_configure_endpoints(int epmask_id, uint32_t mask) diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 43543a1..eaaf125 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -91,7 +91,8 @@ struct pmc_resource_config *config = &pmc_cfg;
if (pmc_soc_get_resources(config) < 0) - die("Unable to get PMC controller resource information!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to get PMC controller resource information!");
/* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index c84f408..356b855 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -98,7 +98,7 @@ reg32 = *ioapic_data; printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); if (reg32 != (1 << 25)) - die("APIC Error\n"); + die_with_post_code(POST_HW_INIT_FAILURE, "APIC Error\n");
printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); for (i=0; i<3; i++) { diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 7d6e4e6..f446708 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -220,7 +220,8 @@
dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); if (!dev) - die("ERROR - IGD device not found!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "ERROR - IGD device not found!");
/* Read TOLUD from Host Bridge offset */ dram_base = sa_get_tolud_base(); diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 595c818..bb1a264 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -38,7 +38,8 @@ while (status & IC_ENABLE_CONTROLLER) { udelay(1); if (--timeout == 0) - die("ERROR - I2C failed to disable!\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "ERROR - I2C failed to disable!\n"); status = regs->ic_enable_status; }
-
Duncan Laurie (Code Review)