Change in coreboot[master]: mb/google/sarien: Program HD Audio SVID/SSID

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/29492

Change subject: mb/google/sarien: Program HD Audio SVID/SSID
......................................................................

mb/google/sarien: Program HD Audio SVID/SSID

Realtek Codec kernel driver requires PCH HD Audio controller to have
subvendor id and subsystem id matched with verb table. Program same
values to make it working.

BUG=N/A
TEST=Boot up on Sarien board and check with kernel driver dmesg to see
ALC3204 or ALC3254.

Change-Id: I3c08da2daf8539864ea3f9aa04ccf488e2844da5
Signed-off-by: Lijian Zhao 
---
M src/mainboard/google/sarien/ramstage.c
A src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h
A src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h
3 files changed, 64 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/29492/1

diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c
index c65104b..cb04fbd 100644
--- a/src/mainboard/google/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/ramstage.c
@@ -16,6 +16,7 @@
 #include <arch/acpi.h>
 #include <soc/ramstage.h>
 #include <variant/gpio.h>
+#include <variant/ssid.h>
 #include <vendorcode/google/chromeos/chromeos.h>

void mainboard_silicon_init_params(FSP_S_CONFIG *params)
@@ -25,6 +26,11 @@

gpio_table = variant_gpio_table(&num_gpios);
    gpio_configure_pads(gpio_table, num_gpios);
+
+	/* Update PCH HDA SVID/SSID */
+	params->SiSsidTablePtr = (uint32_t)ssidtblptr;
+	params->SiNumberOfSsidTableEntry =
+		(sizeof(ssidtblptr) / sizeof(svid_ssid_init_entry));
 }

static void mainboard_enable(struct device *dev)
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h b/src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h
new file mode 100644
index 0000000..66df0cc
--- /dev/null
+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef VARIANT_SSID_H
+#define VARIANT_SSID_H
+
+#include <device/pci_ids.h>
+#include <soc/intel/common/ssid.h>
+
+#define HDA_FUNC	3
+#define ALC_SSID	0x08b6
+
+svid_ssid_init_entry ssidtblptr[] = {
+	{{{PCI_SUBSYSTEM_VENDOR_ID, HDA_FUNC, PCH_DEV_SLOT_LPC, 0, 0, 0, 0 }},
+		{PCI_VENDOR_ID_DELL, ALC_SSID}, 0 },
+};
+
+#endif
diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h b/src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h
new file mode 100644
index 0000000..79bf1c3
--- /dev/null
+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef VARIANT_SSID_H
+#define VARIANT_SSID_H
+
+#include <device/pci_ids.h>
+#include <soc/intel/common/ssid.h>
+
+#define HDA_FUNC	3
+#define ALC_SSID	0x08b8
+
+svid_ssid_init_entry ssidtblptr[] = {
+	{{{PCI_SUBSYSTEM_VENDOR_ID, HDA_FUNC, PCH_DEV_SLOT_LPC, 0, 0, 0, 0 }},
+		{PCI_VENDOR_ID_DELL, ALC_SSID}, 0 },
+};
+
+#endif