Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64009 )
Change subject: nb/amd/agesa/family14: Clean up fx_devs stuff ......................................................................
nb/amd/agesa/family14: Clean up fx_devs stuff
This platform does not support multiple nodes, so get rid of unnecessary complexity. Also remove variables for unused devices.
Change-Id: Ic8475d42627c48336c98afdfe659f3bbfb173c3c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/amd/agesa/family14/northbridge.c 1 file changed, 23 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/64009/1
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index cf67d93..4737b19 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -18,12 +18,8 @@ #include <northbridge/amd/agesa/agesa_helper.h> #include <sb_cimx.h>
-#define FX_DEVS 1 - -static struct device *__f0_dev[FX_DEVS]; -static struct device *__f1_dev[FX_DEVS]; -static struct device *__f2_dev[FX_DEVS]; -static struct device *__f4_dev[FX_DEVS]; +static struct device *__f0_dev; +static struct device *__f1_dev; static unsigned int fx_devs = 0;
static u32 get_io_addr_index(u32 nodeid, u32 linkn) @@ -44,10 +40,10 @@ /* io range allocation */ tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0) << (12 - 4)); //limit - pci_write_config32(__f1_dev[0], reg+4, tempreg); + pci_write_config32(__f1_dev, reg+4, tempreg);
tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? - pci_write_config32(__f1_dev[0], reg, tempreg); + pci_write_config32(__f1_dev, reg, tempreg); }
static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, @@ -57,37 +53,31 @@ u32 tempreg; /* io range allocation */ tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); - pci_write_config32(__f1_dev[0], reg + 4, tempreg); + pci_write_config32(__f1_dev, reg + 4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); - pci_write_config32(__f1_dev[0], reg, tempreg); -} - -static struct device *get_node_pci(u32 nodeid, u32 fn) -{ - return pcidev_on_root(DEV_CDB + nodeid, fn); + pci_write_config32(__f1_dev, reg, tempreg); }
static void get_fx_devs(void) { - int i; - for (i = 0; i < FX_DEVS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i + 1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + if (fx_devs) + return; + + __f0_dev = pcidev_on_root(DEV_CDB, 0); + __f1_dev = pcidev_on_root(DEV_CDB, 1); + + if (__f0_dev == NULL || __f1_dev == NULL) { die("Cannot find 0:0x18.[0|1]\n"); } + + fx_devs = 1; }
static u32 f1_read_config32(unsigned int reg) { if (fx_devs == 0) get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); + return pci_read_config32(__f1_dev, reg); }
static void f1_write_config32(unsigned int reg, u32 value) @@ -97,7 +87,7 @@ get_fx_devs(); for (i = 0; i < fx_devs; i++) { struct device *dev; - dev = __f1_dev[i]; + dev = __f1_dev; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); } @@ -112,7 +102,7 @@ get_fx_devs();
- temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] + temp = pci_read_config32(__f1_dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] if (!(temp & 1)) return 0; // this memory range is not enabled /* @@ -124,7 +114,7 @@ * BKDG address[35:0] <= {DramLimit[35:24], FF_FFFFh} converted as above but * ORed with 0xffff to get real limit before shifting. */ - temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] + temp = pci_read_config32(__f1_dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] *limitk = ((temp & 0x0fff0000) | 0xffff) >> (10 - 8); *limitk += 1; // round up last byte
@@ -161,7 +151,7 @@ res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { struct device *dev; - dev = __f0_dev[nodeid]; + dev = __f0_dev; if (!dev) continue; for (link = 0; !res && (link < 8); link++) { @@ -313,7 +303,7 @@ u32 hole;
if (get_dram_base_limit(0, &basek, &limitk)) { - hole = pci_read_config32(__f1_dev[0], 0xf0); + hole = pci_read_config32(__f1_dev, 0xf0); if (hole & 1) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = 0; // record the node No with hole @@ -471,15 +461,10 @@ limit = f1_read_config32(reg + 0x04); /* Is this register allocated? */ if ((base & 3) != 0) { - unsigned int nodeid, reg_link; + unsigned int reg_link; struct device *reg_dev; - if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base & 0x30); - } else { // io - nodeid = (limit & 0xf) + ((base >> 4) & 0x30); - } reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; + reg_dev = __f0_dev; if (reg_dev) { /* Reserve the resource */ struct resource *res;