Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33146
Change subject: Documentation: How to run coreboot on PC Engines APU2 ......................................................................
Documentation: How to run coreboot on PC Engines APU2
There is no documentation about running coreboot on apu2 platform, so now it describes how to do this.
Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com --- A Documentation/mainboard/pcengines/apu2.jpg A Documentation/mainboard/pcengines/apu2.md A Documentation/mainboard/pcengines/apu2_spi.jpg 3 files changed, 110 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33146/1
diff --git a/Documentation/mainboard/pcengines/apu2.jpg b/Documentation/mainboard/pcengines/apu2.jpg new file mode 100644 index 0000000..d221857 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2.jpg Binary files differ diff --git a/Documentation/mainboard/pcengines/apu2.md b/Documentation/mainboard/pcengines/apu2.md new file mode 100644 index 0000000..a8aa3d2 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2.md @@ -0,0 +1,110 @@ +# PC Engines APU2 + +This page describes how to run coreboot on PC Engines APU2 platform. + +## Technology + +```eval_rst ++------------+---------------------------------------------------------------+ +| CPU | AMD G series GX-412TC | ++------------+---------------------------------------------------------------+ +| CPU core | 1 GHz quad Jaguar core with 64 bit support | +| | 32K data + 32K instruction cache per core, shared 2MB L2 cache| ++------------+---------------------------------------------------------------+ +| DRAM | 2 or 4 GB DDR3-1333 DRAM | ++------------+---------------------------------------------------------------+ +| Boot | From SD card, USB, mSATA SSD, SATA | ++------------+---------------------------------------------------------------+ +| Power | 6 to 12W of 12V power | ++------------+---------------------------------------------------------------+ +| Firmware | coreboot with support for iPXE and USB boot | ++------------+---------------------------------------------------------------+ +``` + +## Required proprietary blobs + +To build working coreboot image some blobs are needed. + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=====================+=============================+=====================+ +| AmdPubKey.bin | AMD Platform Security Processor | Required | ++-----------------+---------------------------------+---------------------+ +| AGESA.bin | AGESA Platform Initialization | Required | ++-----------------+---------------------------------+---------------------+ +| xhci.bin | AMD XHCI controller | Optional | ++-----------------+---------------------------------+---------------------+ +``` + +## Flashing coreboot + +```eval_rst ++---------------------+--------------------------+ +| Type | Value | ++=====================+==========================+ +| Socketed flash | no | ++---------------------+--------------------------+ +| Model | MX25L1606E | ++---------------------+--------------------------+ +| Size | 2 MiB | ++---------------------+--------------------------+ +| Package | SOP-8 | ++---------------------+--------------------------+ +| Write protection | jumper on WP# pin | ++---------------------+--------------------------+ +| Dual BIOS feature | no | ++---------------------+--------------------------+ +| Internal flashing | Super IO Nuvoton NCT5104D| ++---------------------+--------------------------+ +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. It is important to execute +command with a `-c <chipname>` argument: + + flashrom -p internal -c "MX25L1606E" -w coreboot.rom + +### External programming + +**IMPORTANT**: When programming SPI flash, first you need to enter apu2 in S5 +(Soft-off) power state. S5 state can be forced by shorting power button pin on +J2 header. + +The external access to flash chip is available through standard SOP-8 clip or +SOP-8 header next to the flash chip on the board. Notice that not all boards +have a header soldered down originally. Hence, there could be an empty slot with +8 eyelets, so you can solder down a header on your own. The SPI flash chip and +SPI header are marked in the picture below. Also there is SPI header and SPI +flash pin layout included. + +There is no restrictions as to the programmer device. It is only recommended to +flash firmware without supplying power. External programming can be performed, +for example using OrangePi and Armbian. You can exploit linux_spi driver which +provide communication with SPI devices. Example command to program SPI flash +with OrangePi using linux_spi: + + flashrom -f -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 + + +**apu2 platform with marked in SPI header and SPI flash chip** + +![][apu2_flash] + +**SPI header pin layout** + +![][spi_header] + + +## Schematics + +PC Engines APU2 platform schematics are available for free on PC Engines +official site. Depending on the configuration: +- [apu2b](https://www.pcengines.ch/schema/apu2b.pdf) +- [apu2c](https://www.pcengines.ch/schema/apu2c.pdf) +- [apu2d](https://www.pcengines.ch/schema/apu2d.pdf) + +[apu2_flash]: apu2.jpg +[spi_header]: apu2_spi.jpg +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/pcengines/apu2_spi.jpg b/Documentation/mainboard/pcengines/apu2_spi.jpg new file mode 100644 index 0000000..f8a5b58 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2_spi.jpg Binary files differ
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33146 )
Change subject: Documentation: How to run coreboot on PC Engines APU2 ......................................................................
Patch Set 1: Code-Review+1
(2 comments)
https://review.coreboot.org/#/c/33146/1/Documentation/mainboard/pcengines/ap... File Documentation/mainboard/pcengines/apu2.md:
https://review.coreboot.org/#/c/33146/1/Documentation/mainboard/pcengines/ap... PS1, Line 1: # PC Engines APU2 you need to refrence apu2.md from index.md
https://review.coreboot.org/#/c/33146/1/Documentation/mainboard/pcengines/ap... PS1, Line 31: +=====================+=============================+=====================+ table is corrupted here
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33146
to look at the new patch set (#2).
Change subject: Documentation: How to run coreboot on PC Engines APU2 ......................................................................
Documentation: How to run coreboot on PC Engines APU2
There is no documentation about running coreboot on apu2 platform, so now it describes how to do this.
Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com --- M Documentation/mainboard/index.md A Documentation/mainboard/pcengines/apu2.jpg A Documentation/mainboard/pcengines/apu2.md A Documentation/mainboard/pcengines/apu2_spi.jpg 4 files changed, 114 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33146/2
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33146 )
Change subject: Documentation: How to run coreboot on PC Engines APU2 ......................................................................
Patch Set 2: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33146 )
Change subject: Documentation: How to run coreboot on PC Engines APU2 ......................................................................
Patch Set 2: Code-Review-1
(7 comments)
https://review.coreboot.org/#/c/33146/2/Documentation/mainboard/pcengines/ap... File Documentation/mainboard/pcengines/apu2.md:
https://review.coreboot.org/#/c/33146/2/Documentation/mainboard/pcengines/ap... PS2, Line 32: | AmdPubKey.bin | AMD Platform Security Processor | Required | The named file is only of the PSP blobs that get embedded inside the CBFS image. AFAICS the bypass blob is the other compulsory one.
https://review.coreboot.org/#/c/33146/2/Documentation/mainboard/pcengines/ap... PS2, Line 50: | Size | 2 MiB | Model and size here are not correct (seem to be those from apu1).
https://review.coreboot.org/#/c/33146/2/Documentation/mainboard/pcengines/ap... PS2, Line 54: | Write protection | jumper on WP# pin | To tie SPI_WP# ball AU9 of the SoC to GND might actually fry it if we tried to use Quad-IO. 1k0 or 2k2 pull-down might be better for WP#, but I have not experimented with this.
https://review.coreboot.org/#/c/33146/2/Documentation/mainboard/pcengines/ap... PS2, Line 58: | Internal flashing | Super IO Nuvoton NCT5104D| ?
https://review.coreboot.org/#/c/33146/2/Documentation/mainboard/pcengines/ap... PS2, Line 67: flashrom -p internal -c "MX25L1606E" -w coreboot.rom APU2 should detect this correctly without -c parameter ("W25Q64").
https://review.coreboot.org/#/c/33146/2/Documentation/mainboard/pcengines/ap... PS2, Line 80: flash pin layout included. The partial schema picture leaves you with the common confusion about SPI signal directions.
MOSI = J6 SPIDO = U23 SI MISO = J6 SPIDI = U23 SO
Using header J6, do not connect pins 1,7,8. Using clip U23, do not connect pins 3,7,8.
https://review.coreboot.org/#/c/33146/2/Documentation/mainboard/pcengines/ap... PS2, Line 103: official site. Depending on the configuration: The difference in the schematic filename letter is the PCB revision identification. The different configurations (2/4 GiB) have different assembly, but same PCB and schematic.
Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33146
to look at the new patch set (#3).
Change subject: Documentation: How to run coreboot on PC Engines APU2 ......................................................................
Documentation: How to run coreboot on PC Engines APU2
There is no documentation about running coreboot on apu2 platform, so now it describes how to do this.
Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com --- M Documentation/mainboard/index.md A Documentation/mainboard/pcengines/apu2.jpg A Documentation/mainboard/pcengines/apu2.md A Documentation/mainboard/pcengines/apu2_spi.jpg 4 files changed, 120 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33146/3
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33146 )
Change subject: Documentation: How to run coreboot on PC Engines APU2 ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/#/c/33146/3/Documentation/mainboard/pcengines/ap... File Documentation/mainboard/pcengines/apu2.md:
https://review.coreboot.org/#/c/33146/3/Documentation/mainboard/pcengines/ap... PS3, Line 60: | Internal flashing | yes / Super IO | Super IO is not involved with the flashing at all, why is it mentioned here?
https://review.coreboot.org/#/c/33146/3/Documentation/mainboard/pcengines/ap... PS3, Line 110: PC Engines APU2 [platform schematics](https://www.pcengines.ch/schema/apu2b.pdf) Maybe it is better to provide the product page link here or reference the in-production revision D (B was superseded already in 2016).
Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33146
to look at the new patch set (#4).
Change subject: Documentation: How to run coreboot on PC Engines APU2 ......................................................................
Documentation: How to run coreboot on PC Engines APU2
There is no documentation about running coreboot on apu2 platform, so now it describes how to do this.
Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com --- M Documentation/mainboard/index.md A Documentation/mainboard/pcengines/apu2.jpg A Documentation/mainboard/pcengines/apu2.md A Documentation/mainboard/pcengines/apu2_spi.jpg 4 files changed, 120 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33146/4
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33146 )
Change subject: Documentation: How to run coreboot on PC Engines APU2 ......................................................................
Patch Set 4: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33146 )
Change subject: Documentation: How to run coreboot on PC Engines APU2 ......................................................................
Patch Set 4: Code-Review+1
(2 comments)
Thank you!
https://review.coreboot.org/#/c/33146/4//COMMIT_MSG Commit Message:
PS4: I would suggest using present tense in commit messages, e.g.:
Documentation: Add PC Engines apu2
Describe how to run coreboot on the PC Engines apu2 mainboard.
https://review.coreboot.org/#/c/33146/4/Documentation/mainboard/pcengines/ap... File Documentation/mainboard/pcengines/apu2_spi.jpg:
PS4: Excellent picture.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33146 )
Change subject: Documentation: How to run coreboot on PC Engines APU2 ......................................................................
Patch Set 4: Code-Review-1
(1 comment)
https://review.coreboot.org/#/c/33146/4/Documentation/mainboard/pcengines/ap... File Documentation/mainboard/pcengines/apu2.md:
https://review.coreboot.org/#/c/33146/4/Documentation/mainboard/pcengines/ap... PS4, Line 11: | CPU core | 1 GHz quad Jaguar core with 64 bit support | GX-412TC is a Puma microarchitecture not Jaguar
Angel Pons has removed a vote on this change.
Change subject: Documentation: How to run coreboot on PC Engines APU2 ......................................................................
Removed Code-Review+1 by Angel Pons th3fanbus@gmail.com
Hello Kyösti Mälkki, Patrick Rudolph, Angel Pons, build bot (Jenkins), Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33146
to look at the new patch set (#5).
Change subject: Documentation: Add PC Engines apu2 ......................................................................
Documentation: Add PC Engines apu2
Describe how to run coreboot on the PC Engines apu2 mainboard.
Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com --- M Documentation/mainboard/index.md A Documentation/mainboard/pcengines/apu2.jpg A Documentation/mainboard/pcengines/apu2.md A Documentation/mainboard/pcengines/apu2_spi.jpg 4 files changed, 120 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33146/5
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33146 )
Change subject: Documentation: Add PC Engines apu2 ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33146 )
Change subject: Documentation: Add PC Engines apu2 ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/33146/5/Documentation/mainboard/pcengines/ap... File Documentation/mainboard/pcengines/apu2.jpg:
PS5: Can you reduce the file size (e.g. reduce quality settings with jpegoptim)? quality value between 60 and 70 is usually more than enough and I'd guess the image would go down to 50KB or so
Hello Kyösti Mälkki, Patrick Rudolph, Angel Pons, build bot (Jenkins), Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33146
to look at the new patch set (#6).
Change subject: Documentation: Add PC Engines apu2 ......................................................................
Documentation: Add PC Engines apu2
Describe how to run coreboot on the PC Engines apu2 mainboard.
Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com --- M Documentation/mainboard/index.md A Documentation/mainboard/pcengines/apu2.jpg A Documentation/mainboard/pcengines/apu2.md A Documentation/mainboard/pcengines/apu2_spi.jpg 4 files changed, 120 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33146/6
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33146 )
Change subject: Documentation: Add PC Engines apu2 ......................................................................
Patch Set 6: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33146 )
Change subject: Documentation: Add PC Engines apu2 ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/33146/6/Documentation/mainboard/pcengines/ap... File Documentation/mainboard/pcengines/apu2.md:
https://review.coreboot.org/#/c/33146/6/Documentation/mainboard/pcengines/ap... PS6, Line 95: provide provides
Hello Kyösti Mälkki, Patrick Rudolph, Angel Pons, build bot (Jenkins), Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33146
to look at the new patch set (#7).
Change subject: Documentation: Add PC Engines apu2 ......................................................................
Documentation: Add PC Engines apu2
Describe how to run coreboot on the PC Engines apu2 mainboard.
Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com --- M Documentation/mainboard/index.md A Documentation/mainboard/pcengines/apu2.jpg A Documentation/mainboard/pcengines/apu2.md A Documentation/mainboard/pcengines/apu2_spi.jpg 4 files changed, 120 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33146/7
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33146 )
Change subject: Documentation: Add PC Engines apu2 ......................................................................
Patch Set 7: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33146 )
Change subject: Documentation: Add PC Engines apu2 ......................................................................
Documentation: Add PC Engines apu2
Describe how to run coreboot on the PC Engines apu2 mainboard.
Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33146 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M Documentation/mainboard/index.md A Documentation/mainboard/pcengines/apu2.jpg A Documentation/mainboard/pcengines/apu2.md A Documentation/mainboard/pcengines/apu2_spi.jpg 4 files changed, 120 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 205964f..77e84ef 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -86,6 +86,10 @@
- [MS-7707](msi/ms7707/ms7707.md)
+## PC Engines + +- [APU2](pcengines/apu2.md) + ## Roda
- [RK9 Flash Header](roda/rk9/flash_header.md) diff --git a/Documentation/mainboard/pcengines/apu2.jpg b/Documentation/mainboard/pcengines/apu2.jpg new file mode 100644 index 0000000..ae83b9c --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2.jpg Binary files differ diff --git a/Documentation/mainboard/pcengines/apu2.md b/Documentation/mainboard/pcengines/apu2.md new file mode 100644 index 0000000..4a02e12 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2.md @@ -0,0 +1,116 @@ +# PC Engines APU2 + +This page describes how to run coreboot on PC Engines APU2 platform. + +## Technology + +```eval_rst ++------------+---------------------------------------------------------------+ +| CPU | AMD G series GX-412TC | ++------------+---------------------------------------------------------------+ +| CPU core | 1 GHz quad Puma core with 64 bit support | +| | 32K data + 32K instruction cache per core, shared 2MB L2 cache| ++------------+---------------------------------------------------------------+ +| DRAM | 2 or 4 GB DDR3-1333 DRAM | ++------------+---------------------------------------------------------------+ +| Boot | From SD card, USB, mSATA SSD, SATA | ++------------+---------------------------------------------------------------+ +| Power | 6 to 12W of 12V power | ++------------+---------------------------------------------------------------+ +| Firmware | coreboot with support for iPXE and USB boot | ++------------+---------------------------------------------------------------+ +``` + +## Required proprietary blobs + +To build working coreboot image some blobs are needed. + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+=====================+ +| amdfw.rom* | AMD Platform Security Processor | Required | ++-----------------+---------------------------------+---------------------+ +| AGESA.bin | AGESA Platform Initialization | Required | ++-----------------+---------------------------------+---------------------+ +| xhci.bin | AMD XHCI controller | Optional | ++-----------------+---------------------------------+---------------------+ +``` +(*) - package containing all required blobs for PSP. Directory, in which all +blobs are listed and available is: *3rdparty/southbridge/amd/avalon/PSP* + +## Flashing coreboot + +```eval_rst ++---------------------+--------------------------+ +| Type | Value | ++=====================+==========================+ +| Socketed flash | no | ++---------------------+--------------------------+ +| Model | W25Q64 | ++---------------------+--------------------------+ +| Size | 8 MiB | ++---------------------+--------------------------+ +| Package | SOIC-8 | ++---------------------+--------------------------+ +| Write protection | jumper on WP# pin* | ++---------------------+--------------------------+ +| Dual BIOS feature | no | ++---------------------+--------------------------+ +| Internal flashing | yes | ++---------------------+--------------------------+ +``` +(*) - It is used in normal SPI mode, but can be dangerous when using Quad SPI +Flash. Then, pull-down resistors should be considered rather than jumper. + +### Internal programming + +The SPI flash can be accessed using [flashrom]. + + flashrom -p internal -w coreboot.rom + +### External programming + +**IMPORTANT**: When programming SPI flash, first you need to enter apu2 in S5 +(Soft-off) power state. S5 state can be forced by shorting power button pin on +J2 header. + +The external access to flash chip is available through standard SOP-8 clip or +SOP-8 header next to the flash chip on the board. Notice that not all boards +have a header soldered down originally. Hence, there could be an empty slot with +8 eyelets, so you can solder down a header on your own. The SPI flash chip and +SPI header are marked in the picture below. Also there is SPI header and SPI +flash pin layout included. Depend on using header or clip there are important +rules: +- using header J6 - don't connect 1,7,8 pins +- using clip U23 - don't connect 3,7,8 pins + +Also signatures at the schematic can be ambiguous: +- J6 SPIDI = U23 SO = MISO +- J6 SPIDO = U23 SI = MOSI + +There is no restrictions as to the programmer device. It is only recommended to +flash firmware without supplying power. External programming can be performed, +for example using OrangePi and Armbian. You can exploit linux_spi driver which +provides communication with SPI devices. Example command to program SPI flash +with OrangePi using linux_spi: + + flashrom -f -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 + +**apu2 platform with marked in SPI header and SPI flash chip** + +![][apu2_flash] + +**SPI header pin layout** + +![][spi_header] + +## Schematics + +PC Engines APU2 [platform schematics](https://pcengines.ch/schema/apu2d.pdf) +are available for free on PC Engines official site. Both configurations +(2GB/4GB) have the same PCB and schematic. + +[apu2_flash]: apu2.jpg +[spi_header]: apu2_spi.jpg +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/pcengines/apu2_spi.jpg b/Documentation/mainboard/pcengines/apu2_spi.jpg new file mode 100644 index 0000000..f8a5b58 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2_spi.jpg Binary files differ
-
Angel Pons (Code Review) -
Kyösti Mälkki (Code Review)
-
Michał Żygowski (Code Review)
-
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)
-
Piotr Kleinschmidt (Code Review)