Patch set 2:Code-Review -1

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7 comments:

• File Documentation/mainboard/pcengines/apu2.md:

  • Patch Set #2, Line 32: | AmdPubKey.bin | AMD Platform Security Processor | Required |

    The named file is only of the PSP blobs that get embedded inside the CBFS image. AFAICS the bypass blob is the other compulsory one.

  • Patch Set #2, Line 50: | Size | 2 MiB |

    Model and size here are not correct (seem to be those from apu1).

  • Patch Set #2, Line 54: | Write protection | jumper on WP# pin |

    To tie SPI_WP# ball AU9 of the SoC to GND might actually fry it if we tried to use Quad-IO. 1k0 or 2k2 pull-down might be better for WP#, but I have not experimented with this.

  • Patch Set #2, Line 58: | Internal flashing | Super IO Nuvoton NCT5104D|

    ?

  • Patch Set #2, Line 67: flashrom -p internal -c "MX25L1606E" -w coreboot.rom

    APU2 should detect this correctly without -c parameter ("W25Q64").

  • Patch Set #2, Line 80: flash pin layout included.

    The partial schema picture leaves you with the common confusion about SPI signal directions.

    MOSI = J6 SPIDO = U23 SI
    MISO = J6 SPIDI = U23 SO

    Using header J6, do not connect pins 1,7,8.
    Using clip U23, do not connect pins 3,7,8.

  • Patch Set #2, Line 103: official site. Depending on the configuration:

    The difference in the schematic filename letter is the PCB revision identification. The different configurations (2/4 GiB) have different assembly, but same PCB and schematic.

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