Change in coreboot[master]: soc/intel/alderlake, mb/google/brya: Update Type-C USB2 port config

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Maulik V Vaghela, Ravindra, Sridhar Siricilla, Mark Hsieh, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61586 )

Change subject: soc/intel/alderlake, mb/google/brya: Update Type-C USB2 port config
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Patch Set 6:

(2 comments)

Patchset:

PS6: 
c

File src/soc/intel/alderlake/include/soc/usb.h:

https://review.coreboot.org/c/coreboot/+/61586/comment/cae71c40_898a23c2 
PS6, Line 98: #define USB2_PORT_MAX_TYPE_C(pin) { \
            : 	.enable        = 1, \
            : 	.ocpin         = (pin), \
            : 	.tx_bias       = USB2_BIAS_56P3MV, \
            : 	.tx_emp_enable = USB2_PRE_EMP_ON, \
            : 	.pre_emp_bias  = USB2_BIAS_56P3MV, \
            : 	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
            : 	.type_c        = 1, \
            : }
            : 
I guess we could split this into two macros,
USB2_PORT_MAX_TYPE_C
and
USB2_PORT_MAX
which could be done in separate CLs. WDYT?