Change in coreboot[master]: soc/intel/skylake: acpi: drop HWP's dependency on EIST

[Michael Niewöhner (Code Review)]

Hello  Felix Singer, build bot (Jenkins), Matt Delco, Nico Huber, Patrick Georgi, Paul Menzel, Subrata Banik, Arthur Heymans, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44137

to look at the new patch set (#5).

Change subject: soc/intel/skylake: acpi: drop HWP's dependency on EIST
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soc/intel/skylake: acpi: drop HWP's dependency on EIST

Enhanced Intel SpeedStep Technology (EIST) and Intel Speed Shift
Technology (ISST) - also know as HWP - are two independent mechanisms
for controlling voltage and frequency based on performance hints.

When HWP is enabled, it overrides the software-based EIST. It does not
depend on EIST, though, but can be enabled on its own.

Break up that currently existing dependency in ACPI generation code.

It was tested that HWP can be enabled and gets used by the Linux pstate
cpufreq driver. With HWP disabled, the frequency does not decrease, even
not in powersave mode. After enabling HWP the frequency changed in
relation to the current workload. (Test device: Acer ES1-572)

Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda
Signed-off-by: Michael Niewöhner 
---
M src/soc/intel/skylake/acpi.c
1 file changed, 5 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44137/5