Change in coreboot[master]: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power ...

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Jamie Chen, Tim Wawrzynczak.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63675 )

Change subject: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption
......................................................................

Patch Set 5: Code-Review+2

(2 comments)

File src/soc/intel/jasperlake/chip.h:

https://review.coreboot.org/c/coreboot/+/63675/comment/282ed3af_e18fc1b9 
PS5, Line 428:  * Setting this on a system that supports S0i3 (set xtalsdqdis [Bit 22] in
             : 	 * cppmvric1 register to 0) will break CNVI timing.
> The xtalsdqdis bit can be set or clear by ASL code or OS code. […]

Ack

File src/soc/intel/jasperlake/finalize.c:

https://review.coreboot.org/c/coreboot/+/63675/comment/cacba913_21b1b413 
PS5, Line 63: 		if (config->cnvi_reduce_s0ix_pwr_usage) {
> This is only for system with CNVi module to work around and keeping this enabled will not impact the […]

Ack