Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26860
Change subject: nb/intel/i945: Add default case for CPCTL ......................................................................
nb/intel/i945: Add default case for CPCTL
The default MCHBAR8(CPCTL) is 0x80. This value is also used for on desktop with FSB800.
Change-Id: Ifb343ff45ccb2c10a6d2ac294d80add67dd4a1d6 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/raminit.c 1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/26860/1
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 6719961..8405134 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1622,11 +1622,13 @@ /* Only write the lower byte */ switch (sysinfo->fsb_frequency) { case 400: - MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */ + MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */ case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */ case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */ + default: + MCHBAR8(CPCTL) = 0x80; }
MCHBAR16(CPCTL) &= ~(1 << 11);