Change in coreboot[master]: [WIP]soc/intel/alderlake: Update meminit code due to upd changes FSP ...

[Bora Guvendik (Code Review)]

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54036 )

Change subject: [WIP]soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwards
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[WIP]soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwards

DisableDimmMc0Ch0 upds changed to DisableMc0Ch0 in new FSP releases. The definition
of the upd also changed. Changed FSP meminit code to work based on new definition of the UPDs.

Before:
0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs

After:
0:Enable, 1:Disable

TEST=Boot to OS

Signed-off-by: Bora Guvendik 
Change-Id: I5af11ae99db3bbe3373a9bd4ce36453b58d62fec
---
M src/soc/intel/alderlake/meminit.c
1 file changed, 14 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/54036/1

diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index 33f26da..e6abb38 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -146,16 +146,27 @@

mem_cfg->MemorySpdDataLen = data->spd_len;

+	/* Disable all channels initially */
+	mem_cfg->DisableMc0Ch0 = 1;
+	mem_cfg->DisableMc0Ch1 = 1;
+	mem_cfg->DisableMc0Ch2 = 1;
+	mem_cfg->DisableMc0Ch3 = 1;
+	mem_cfg->DisableMc1Ch0 = 1;
+	mem_cfg->DisableMc1Ch1 = 1;
+	mem_cfg->DisableMc1Ch2 = 1;
+	mem_cfg->DisableMc1Ch3 = 1;
+
    for (ch = 0; ch < MRC_CHANNELS; ch++) {
    	uint8_t *disable_dimm_ptr = disable_dimm_upds[ch];
-		*disable_dimm_ptr = 0;

for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
    		uint32_t *spd_ptr = spd_upds[ch][dimm];

*spd_ptr = data->spd[ch][dimm];
-			if (!*spd_ptr)
-				*disable_dimm_ptr |= BIT(dimm);
+			if (*spd_ptr) {
+				*disable_dimm_ptr = 0;
+				break;
+			}
    	}
    }
 }