New patch to review for coreboot: 007e33c armv7: update sync barrier usage in dcache_op_set_way()

[David Hendricks]

David Hendricks ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2929

-gerrit

commit 007e33c7cbb43d68d4ce2ce2a3a4e1f9b0a1cb71
Author: David Hendricks 
Date:   Tue Mar 26 21:34:01 2013 -0700

armv7: update sync barrier usage in dcache_op_set_way()

This moves the dsb() before the loop to sync any outstanding memory
    accesses, and adds an isb() after the loop to ensure all outstanding
    instructions are completed.

Change-Id: I1a11b39f104ae780370cfd2db3badcf4e91dc017
    Signed-off-by: David Hendricks 
---
 src/arch/armv7/lib/cache.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c
index 0e28ac4..3cd0e0a 100644
--- a/src/arch/armv7/lib/cache.c
+++ b/src/arch/armv7/lib/cache.c
@@ -111,6 +111,8 @@ static void dcache_op_set_way(enum dcache_op op)
    /* FIXME: do we need to use CTR.DminLine here? */
    linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4;

+	dsb();
+
    /*
     * Set/way operations require an interesting bit packing. See section
     * B4-35 in the ARMv7 Architecture Reference Manual:
@@ -144,8 +146,7 @@ static void dcache_op_set_way(enum dcache_op op)
    		}
    	}
    }
-
-	dsb();
+	isb();
 }

void dcache_clean_invalidate_all(void)