Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31119
Change subject: mb/intel/icelake_rvp/../icl_y: Enable SaGv ......................................................................
mb/intel/icelake_rvp/../icl_y: Enable SaGv
This patch enables SaGv on Intel ICL-Y RVP board.
TEST=Able to build and boot to Chrome OS.
Change-Id: Ic3ed94d47ddc7fd70bf3de1db15fe574029df856 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/31119/1
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index 0972c29..4f41308 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -13,7 +13,7 @@ register "gpe0_dw2" = "GPP_E"
# FSP configuration - register "SaGv" = "SaGv_Disabled" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1"
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31119 )
Change subject: mb/intel/icelake_rvp/../icl_y: Enable SaGv ......................................................................
Patch Set 1: Code-Review+1
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31119 )
Change subject: mb/intel/icelake_rvp/../icl_y: Enable SaGv ......................................................................
Patch Set 1: Code-Review+2
Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31119 )
Change subject: mb/intel/icelake_rvp/../icl_y: Enable SaGv ......................................................................
mb/intel/icelake_rvp/../icl_y: Enable SaGv
This patch enables SaGv on Intel ICL-Y RVP board.
TEST=Able to build and boot to Chrome OS.
Change-Id: Ic3ed94d47ddc7fd70bf3de1db15fe574029df856 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/31119 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Duncan Laurie dlaurie@chromium.org --- M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index 0972c29..4f41308 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -13,7 +13,7 @@ register "gpe0_dw2" = "GPP_E"
# FSP configuration - register "SaGv" = "SaGv_Disabled" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1"
-
Duncan Laurie (Code Review) -
Paul Menzel (Code Review)
-
Subrata Banik (Code Review)