Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50290 )
Change subject: mb/google/volteer: Enable external bypass, clkgate & phygate ......................................................................
mb/google/volteer: Enable external bypass, clkgate & phygate
This change sets the soc config options for external_bypass, external_clk_gate and external_phy_gate.
BUG=b:177821896 TEST=Build coreboot for volteer
Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50290 Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Sukumar Ghorai sukumar.ghorai@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Sukumar Ghorai: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ccde132..6a826c0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -255,6 +255,15 @@ # Enable DPTF register "dptf_enable" = "1"
+ # Enable External Bypass + register "external_bypass" = "1" + + # Enable External Clk Gate + register "external_clk_gated" = "1" + + # Enable External Phy Gate + register "external_phy_gated" = "1" + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 38,