[M] Change in coreboot[master]: soc/amd/mendocino: Remove the SPL DPTC parameter

[Chris Wang (Code Review)]

Attention is currently required from: Frank Wu, Jason Glenesk, Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Isaac Lee, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held.

Chris Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73124 )

Change subject: soc/amd/mendocino: Remove the SPL DPTC parameter
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Patch Set 6:

(1 comment)

File src/mainboard/google/skyrim/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/73124/comment/26bae950_c7348e35 
PS6, Line 263: # Remove the sustained_power_limit_mW when STT is enabled
             : 	register "sustained_power_limit_mW"              = "15000"
> I'm leaning towards Frank's suggestion, since the current comment is not entirely accurate. […]

I submit another CL for moving `sustained_power_limit_mW` to `overridetree.cb`  Would you help take a look ? https://review.coreboot.org/c/coreboot/+/73426.