Change in coreboot[master]: amd/stoneyridge: Add BIOS RAM R/W functions

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22649

Change subject: amd/stoneyridge: Add BIOS RAM R/W functions
......................................................................

amd/stoneyridge: Add BIOS RAM R/W functions

The internal FCH contains 256 bytes of "BiosRam" that maintains its
state until RSMRST# is asserted or standby power is lost.  Add functions
to support read and write operations.

Change-Id: Ibf4766a2ded0968e46380dca63b1dcf59afb9cfa
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/sb_util.c
2 files changed, 55 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/22649/1

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 29230fc..1cecda6 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -294,6 +294,12 @@
 void smi_write8(uint8_t offset, uint8_t value);
 void smi_write16(uint8_t offset, uint16_t value);
 void smi_write32(uint8_t offset, uint32_t value);
+uint8_t biosram_read8(uint8_t offset);
+void biosram_write8(uint8_t offset, uint8_t value);
+uint32_t biosram_read16(uint8_t offset);
+void biosram_write16(uint8_t offset, uint16_t value);
+uint32_t biosram_read32(uint8_t offset);
+void biosram_write32(uint8_t offset, uint32_t value);
 uint16_t pm_acpi_pm_cnt_blk(void);
 uint16_t pm_acpi_pm_evt_blk(void);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c
index 36dccaa..0774eae 100644
--- a/src/soc/amd/stoneyridge/sb_util.c
+++ b/src/soc/amd/stoneyridge/sb_util.c
@@ -71,11 +71,60 @@
    return read8((void *)(APU_SMI_BASE + offset));
 }

+
 void smi_write8(uint8_t offset, uint8_t value)
 {
    write8((void *)(APU_SMI_BASE + offset), value);
 }

+uint8_t biosram_read8(uint8_t offset)
+{
+	outb(offset, BIOSRAM_INDEX);
+	return inb(BIOSRAM_DATA);
+}
+
+void biosram_write8(uint8_t offset, uint8_t value)
+{
+	outb(offset, BIOSRAM_INDEX);
+	outb(value, BIOSRAM_DATA);
+}
+
+uint32_t biosram_read16(uint8_t offset)
+{
+	int i;
+	uint32_t value = 0;
+	for (i = 1 ; i >= 0 ; i--)
+		value = (value << 8) | biosram_read8(offset + i);
+	return value;
+}
+
+uint32_t biosram_read32(uint8_t offset)
+{
+	int i;
+	uint32_t value = 0;
+	for (i = 3 ; i >= 0 ; i--)
+		value = (value << 8) | biosram_read8(offset + i);
+	return value;
+}
+
+void biosram_write16(uint8_t offset, uint16_t value)
+{
+	int i;
+	for (i = 0 ; i < 2 ; i++) {
+		biosram_write8(offset + i, value & 0xff);
+		value >>= 8;
+	}
+}
+
+void biosram_write32(uint8_t offset, uint32_t value)
+{
+	int i;
+	for (i = 0 ; i < 4 ; i++) {
+		biosram_write8(offset + i, value & 0xff);
+		value >>= 8;
+	}
+}
+
 uint16_t pm_acpi_pm_cnt_blk(void)
 {
    return pm_read16(PM1_CNT_BLK);