Change in coreboot[master]: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification

[Krishna P Bhat D (Code Review)]

Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49012 )

Change subject: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
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Patch Set 5:

(3 comments)

https://review.coreboot.org/c/coreboot/+/49012/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/49012/4//COMMIT_MSG@15 
PS4, Line 15: s0ix works on drawcia and USB wake from s0ix works fine.
> Can you please confirm if the USB3 HID device is able to wakeup the system?

We have not checked with USB3 HID device, could not get hold of one.

https://review.coreboot.org/c/coreboot/+/49012/4/src/soc/intel/jasperlake/fi... 
File src/soc/intel/jasperlake/finalize.c:

https://review.coreboot.org/c/coreboot/+/49012/4/src/soc/intel/jasperlake/fi... 
PS4, Line 69: System enters s0ix with USB keyboard connected. However, it is not waking up
            : 		 * from USB keyboard events.
> This part of comment is probably not relevant to what the disqualification bit is doing and can be r […]

Done

https://review.coreboot.org/c/coreboot/+/49012/4/src/soc/intel/jasperlake/fi... 
PS4, Line 69: /* System enters s0ix with USB keyboard connected. However, it is not waking up
            : 		 * from USB keyboard events. (b:175767084)
            : 		 *
            : 		 * Enable USBSUSPGQDIS qualification to ensure USB2 PHY SUS is power gated
            : 		 * before entering s0ix */
> Coreboot preferred style for multi-line comments - https://doc.coreboot.org/coding_style. […]

Done