Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44360 )
Change subject: doc/mb/ocp: update Delta Lake documentation ......................................................................
doc/mb/ocp: update Delta Lake documentation
Update Delta Lake documentation following ww30 to ww33 build/test/release cycle.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I9bb3a4daa423503d487045f2f069a43d2cc09129 --- M Documentation/mainboard/ocp/deltalake.md 1 file changed, 30 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/44360/1
diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index c4c3284..97b1f42 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -1,7 +1,8 @@ # OCP Delta Lake
This page describes coreboot support status for the [OCP] (Open Compute Project) -Delta Lake server platform. +Delta Lake server platform. This page is updated following each 4-weeks +build/test/release cycle.
## Introduction
@@ -22,7 +23,7 @@ - FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package) is not yet available to the public. It will be made public some time after the MP (Mass Production) of CooperLake Scalable Processor when the FSP is mature. -- Microcode: Not yet available to the public. +- Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git. - ME binary: Not yet available to the public.
## Payload @@ -55,26 +56,43 @@ - Type 2 -- Baseboard Information - Type 3 -- System Enclosure or Chassis - Type 4 -- Processor Information + - Type 7 -- Cache Information - Type 8 -- Port Connector Information - Type 9 -- PCI Slot Information - Type 11 -- OEM String - Type 13 -- BIOS Language Information - - Type 16 -- Physical Memory Array - - Type 19 -- Memory Array Mapped Address + - Type 32 -- System Boot Information + - Type 38 -- IPMI Device Information - Type 127 -- End-of-Table - - BMC integration: - BMC readiness check - IPMI commands - watchdog timer - POST complete pin acknowledgement + - Check BMC version: ipmidump -device - SEL record generation - Early serial output - port 80h direct to GPIO -- ACPI tables: APIC/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT +- ACPI tables: APIC/DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT - Skipping memory training upon subsequent reboots by using MRC cache - BMC crash dump - Error injection through ITP +- Versions + - Check FSP version: cbmem | grep LB_TAG_PLATFORM_BLOB_VERSION + - Check Microcode version: cat /proc/cpuinfo | grep microcode +- Devices: + - Boot drive + - NIC card + - All 5 data drives +- Power button +- localboot +- netboot from IPv6 + +## Stress/performance tests passed +- OS warm reboot overnight (6 hours) +- Mprime test (6 hours) +- MLC (Intel Memory Latency Check) +- Linkpack
## Firmware configurations [ChromeOS VPD] is used to store most of the firmware configurations. @@ -84,29 +102,24 @@ VPD variables supported are: - firmware_version: This variable holds overall firmware version. coreboot uses that value to populate smbios type 1 version field. +- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h.
## Known issues -- Even though CPX-SP FSP is based on FSP 2.2 framework, it does not - support FSP_USES_CB_STACK. An IPS ticket is filed with Intel. -- VT-d is not supported. An IPS ticket is filed with Intel. -- PCIe bifuration is not supported. An IPS ticket is filed with Intel. - ME based power capping. This is a bug in ME. An IPS ticket is filed with Intel. -- RO_VPD region as well as other RO regions are not write protected. - HECI is not set up correctly, so BMC is not able to get PCH and DIMM - temperature sensor readings. + temperature sensor readings. An IPS ticket is filed.
## Feature gaps -- Delta Lake DVT is not supported, as we only have Delta Lake EVT servers - at the moment. - SMBIOS: - - Type 7 -- Cache Information + - Type 16 -- Physical Memory Array - Type 17 -- Memory Device + - Type 19 -- Memory Array Mapped Address - Type 38 -- IPMI Device Information - Type 41 -- Onboard Devices Extended Information -- ACPI: - - DMAR +- Hardware error injection, detection, reporting - PFR/CBnT +- RO_VPD region as well as other RO regions are not write protected.
## Technology
Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Johnny Lin, Paul Menzel, Angel Pons, Bryant Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44360
to look at the new patch set (#2).
Change subject: doc/mb/ocp: update Delta Lake documentation ......................................................................
doc/mb/ocp: update Delta Lake documentation
Update Delta Lake documentation following ww30 to ww33 build/test/release cycle.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I9bb3a4daa423503d487045f2f069a43d2cc09129 --- M Documentation/mainboard/ocp/deltalake.md 1 file changed, 31 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/44360/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44360 )
Change subject: doc/mb/ocp: update Delta Lake documentation ......................................................................
Patch Set 2: Code-Review+1
(4 comments)
https://review.coreboot.org/c/coreboot/+/44360/2/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/44360/2/Documentation/mainboard/ocp... PS2, Line 26: github.com:otcshare/Intel-Generic-Microcode.git https://github.com/otcshare/Intel-Generic-Microcode
Looks like it's not available to the public yet. I guess one needs a NDA?
https://review.coreboot.org/c/coreboot/+/44360/2/Documentation/mainboard/ocp... PS2, Line 27: Not yet available to the public. random thought: I wonder if the Ignition firmware for Purley would work here as well.
https://www.phoronix.com/scan.php?page=news_item&px=Intel-ME-CXL-Ignitio...
https://review.coreboot.org/c/coreboot/+/44360/2/Documentation/mainboard/ocp... PS2, Line 118: - Type 38 -- IPMI Device Information It's on line 65 too
https://review.coreboot.org/c/coreboot/+/44360/2/Documentation/mainboard/ocp... PS2, Line 132: C627 `C620 Series` ?
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44360 )
Change subject: doc/mb/ocp: update Delta Lake documentation ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44360/2/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/44360/2/Documentation/mainboard/ocp... PS2, Line 26: github.com:otcshare/Intel-Generic-Microcode.git
You are most likely right. You need to send an email to an Intel address (sorry I am not able to find the details anymore), and ask for permission to be granted. I believe any NDA (not specific to a SoC) can get you access to all microcodes.
https://review.coreboot.org/c/coreboot/+/44360/2/Documentation/mainboard/ocp... PS2, Line 27: Not yet available to the public.
random thought: I wonder if the Ignition firmware for Purley would work here as well. […]
I do not know. I asked Intel. If they say yes, we should give it a try.
https://review.coreboot.org/c/coreboot/+/44360/2/Documentation/mainboard/ocp... PS2, Line 118: - Type 38 -- IPMI Device Information
It's on line 65 too
Thank you for spotting this.
https://review.coreboot.org/c/coreboot/+/44360/2/Documentation/mainboard/ocp... PS2, Line 132: C627
`C620 Series` ?
Done
Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Johnny Lin, Paul Menzel, Angel Pons, Bryant Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44360
to look at the new patch set (#3).
Change subject: doc/mb/ocp: update Delta Lake documentation ......................................................................
doc/mb/ocp: update Delta Lake documentation
Update Delta Lake documentation following ww30 to ww33 build/test/release cycle.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I9bb3a4daa423503d487045f2f069a43d2cc09129 --- M Documentation/mainboard/ocp/deltalake.md 1 file changed, 31 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/44360/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44360 )
Change subject: doc/mb/ocp: update Delta Lake documentation ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44360/2/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/44360/2/Documentation/mainboard/ocp... PS2, Line 26: github.com:otcshare/Intel-Generic-Microcode.git
You are most likely right. […]
Ack
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44360 )
Change subject: doc/mb/ocp: update Delta Lake documentation ......................................................................
doc/mb/ocp: update Delta Lake documentation
Update Delta Lake documentation following ww30 to ww33 build/test/release cycle.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I9bb3a4daa423503d487045f2f069a43d2cc09129 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44360 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M Documentation/mainboard/ocp/deltalake.md 1 file changed, 31 insertions(+), 19 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index c4c3284..0bc5735 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -1,7 +1,8 @@ # OCP Delta Lake
This page describes coreboot support status for the [OCP] (Open Compute Project) -Delta Lake server platform. +Delta Lake server platform. This page is updated following each 4-weeks +build/test/release cycle.
## Introduction
@@ -22,7 +23,7 @@ - FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package) is not yet available to the public. It will be made public some time after the MP (Mass Production) of CooperLake Scalable Processor when the FSP is mature. -- Microcode: Not yet available to the public. +- Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git. - ME binary: Not yet available to the public.
## Payload @@ -55,26 +56,43 @@ - Type 2 -- Baseboard Information - Type 3 -- System Enclosure or Chassis - Type 4 -- Processor Information + - Type 7 -- Cache Information - Type 8 -- Port Connector Information - Type 9 -- PCI Slot Information - Type 11 -- OEM String - Type 13 -- BIOS Language Information - - Type 16 -- Physical Memory Array - - Type 19 -- Memory Array Mapped Address + - Type 32 -- System Boot Information + - Type 38 -- IPMI Device Information - Type 127 -- End-of-Table - - BMC integration: - BMC readiness check - IPMI commands - watchdog timer - POST complete pin acknowledgement + - Check BMC version: ipmidump -device - SEL record generation - Early serial output - port 80h direct to GPIO -- ACPI tables: APIC/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT +- ACPI tables: APIC/DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT - Skipping memory training upon subsequent reboots by using MRC cache - BMC crash dump - Error injection through ITP +- Versions + - Check FSP version: cbmem | grep LB_TAG_PLATFORM_BLOB_VERSION + - Check Microcode version: cat /proc/cpuinfo | grep microcode +- Devices: + - Boot drive + - NIC card + - All 5 data drives +- Power button +- localboot +- netboot from IPv6 + +## Stress/performance tests passed +- OS warm reboot overnight (6 hours) +- Mprime test (6 hours) +- MLC (Intel Memory Latency Check) +- Linkpack
## Firmware configurations [ChromeOS VPD] is used to store most of the firmware configurations. @@ -84,29 +102,23 @@ VPD variables supported are: - firmware_version: This variable holds overall firmware version. coreboot uses that value to populate smbios type 1 version field. +- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h.
## Known issues -- Even though CPX-SP FSP is based on FSP 2.2 framework, it does not - support FSP_USES_CB_STACK. An IPS ticket is filed with Intel. -- VT-d is not supported. An IPS ticket is filed with Intel. -- PCIe bifuration is not supported. An IPS ticket is filed with Intel. - ME based power capping. This is a bug in ME. An IPS ticket is filed with Intel. -- RO_VPD region as well as other RO regions are not write protected. - HECI is not set up correctly, so BMC is not able to get PCH and DIMM - temperature sensor readings. + temperature sensor readings. An IPS ticket is filed.
## Feature gaps -- Delta Lake DVT is not supported, as we only have Delta Lake EVT servers - at the moment. - SMBIOS: - - Type 7 -- Cache Information + - Type 16 -- Physical Memory Array - Type 17 -- Memory Device - - Type 38 -- IPMI Device Information + - Type 19 -- Memory Array Mapped Address - Type 41 -- Onboard Devices Extended Information -- ACPI: - - DMAR +- Hardware error injection, detection, reporting - PFR/CBnT +- RO_VPD region as well as other RO regions are not write protected.
## Technology
@@ -116,7 +128,7 @@ +------------------------+---------------------------------------------+ | BMC | Aspeed AST 2500 | +------------------------+---------------------------------------------+ -| PCH | Intel Lewisburg C621 | +| PCH | Intel Lewisburg C620 Series | +------------------------+---------------------------------------------+ ```
-
Angel Pons (Code Review) -
Jonathan Zhang (Code Review)