Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
soc/intel/jasperlake: Add Jasper Lake SoC support
This is a copy patch from Tiger Lake SoC code.
The only changes done on top of copy is changing below configs: 1. SOC_INTEL_TIGERLAKE -> SOC_INTEL_TIGERLAKE_COPY 2. SOC_INTEL_JASPERLAKE -> SOC_INTEL_JASPERLAKE_COPY 3. SOC_INTEL_TIGERLAKE_BASE -> SOC_INTEL_TIGERLAKE_BASE
We started with initial assumption that jsl and tgl can co-exist. But now we see the SoC code in Tiger Lake is relying on too many compile time directive to make two SoCs co-exist.
BUG=b:150217037
Change-Id: I9c33f478a2f8ed5e2d8e7815821d13044d35d388 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- A src/soc/intel/jasperlake/Kconfig A src/soc/intel/jasperlake/Makefile.inc A src/soc/intel/jasperlake/acpi.c A src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl A src/soc/intel/jasperlake/acpi/gpio.asl A src/soc/intel/jasperlake/acpi/gpio_op.asl A src/soc/intel/jasperlake/acpi/ipu.asl A src/soc/intel/jasperlake/acpi/ish.asl A src/soc/intel/jasperlake/acpi/pch_glan.asl A src/soc/intel/jasperlake/acpi/pch_hda.asl A src/soc/intel/jasperlake/acpi/pci_irqs.asl A src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl A src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl A src/soc/intel/jasperlake/acpi/pcie.asl A src/soc/intel/jasperlake/acpi/platform.asl A src/soc/intel/jasperlake/acpi/pmc.asl A src/soc/intel/jasperlake/acpi/scs.asl A src/soc/intel/jasperlake/acpi/serialio.asl A src/soc/intel/jasperlake/acpi/smbus.asl A src/soc/intel/jasperlake/acpi/southbridge.asl A src/soc/intel/jasperlake/acpi/xhci.asl A src/soc/intel/jasperlake/acpi/xhci_jsl.asl A src/soc/intel/jasperlake/acpi/xhci_tgl.asl A src/soc/intel/jasperlake/bootblock/bootblock.c A src/soc/intel/jasperlake/bootblock/cpu.c A src/soc/intel/jasperlake/bootblock/pch.c A src/soc/intel/jasperlake/bootblock/report_platform.c A src/soc/intel/jasperlake/chip.c A src/soc/intel/jasperlake/chip.h A src/soc/intel/jasperlake/cpu.c A src/soc/intel/jasperlake/elog.c A src/soc/intel/jasperlake/espi.c A src/soc/intel/jasperlake/finalize.c A src/soc/intel/jasperlake/fsp_params_jsl.c A src/soc/intel/jasperlake/fsp_params_tgl.c A src/soc/intel/jasperlake/gpio_jsl.c A src/soc/intel/jasperlake/gpio_tgl.c A src/soc/intel/jasperlake/graphics.c A src/soc/intel/jasperlake/gspi.c A src/soc/intel/jasperlake/i2c.c A src/soc/intel/jasperlake/include/soc/bootblock.h A src/soc/intel/jasperlake/include/soc/cpu.h A src/soc/intel/jasperlake/include/soc/espi.h A src/soc/intel/jasperlake/include/soc/gpe.h A src/soc/intel/jasperlake/include/soc/gpio.h A src/soc/intel/jasperlake/include/soc/gpio_defs.h A src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h A src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h A src/soc/intel/jasperlake/include/soc/iomap.h A src/soc/intel/jasperlake/include/soc/irq.h A src/soc/intel/jasperlake/include/soc/irq_jsl.h A src/soc/intel/jasperlake/include/soc/irq_tgl.h A src/soc/intel/jasperlake/include/soc/itss.h A src/soc/intel/jasperlake/include/soc/me.h A src/soc/intel/jasperlake/include/soc/meminit_jsl.h A src/soc/intel/jasperlake/include/soc/meminit_tgl.h A src/soc/intel/jasperlake/include/soc/msr.h A src/soc/intel/jasperlake/include/soc/nvs.h A src/soc/intel/jasperlake/include/soc/p2sb.h A src/soc/intel/jasperlake/include/soc/pch.h A src/soc/intel/jasperlake/include/soc/pci_devs.h A src/soc/intel/jasperlake/include/soc/pcr_ids.h A src/soc/intel/jasperlake/include/soc/pm.h A src/soc/intel/jasperlake/include/soc/pmc.h A src/soc/intel/jasperlake/include/soc/ramstage.h A src/soc/intel/jasperlake/include/soc/romstage.h A src/soc/intel/jasperlake/include/soc/serialio.h A src/soc/intel/jasperlake/include/soc/smbus.h A src/soc/intel/jasperlake/include/soc/soc_chip.h A src/soc/intel/jasperlake/include/soc/systemagent.h A src/soc/intel/jasperlake/include/soc/usb.h A src/soc/intel/jasperlake/lockdown.c A src/soc/intel/jasperlake/meminit_jsl.c A src/soc/intel/jasperlake/meminit_tgl.c A src/soc/intel/jasperlake/p2sb.c A src/soc/intel/jasperlake/pmc.c A src/soc/intel/jasperlake/pmutil.c A src/soc/intel/jasperlake/reset.c A src/soc/intel/jasperlake/romstage/Makefile.inc A src/soc/intel/jasperlake/romstage/fsp_params_jsl.c A src/soc/intel/jasperlake/romstage/fsp_params_tgl.c A src/soc/intel/jasperlake/romstage/pch.c A src/soc/intel/jasperlake/romstage/romstage.c A src/soc/intel/jasperlake/romstage/systemagent.c A src/soc/intel/jasperlake/sd.c A src/soc/intel/jasperlake/smihandler.c A src/soc/intel/jasperlake/smmrelocate.c A src/soc/intel/jasperlake/spi.c A src/soc/intel/jasperlake/systemagent.c A src/soc/intel/jasperlake/uart.c 93 files changed, 10,462 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/39823/1
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39823/1/src/soc/intel/jasperlake/in... File src/soc/intel/jasperlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/39823/1/src/soc/intel/jasperlake/in... PS1, Line 20: void mainboard_memory_init_params(FSPM_UPD *mupd); need consistent spacing around '*' (ctx:WxV)
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/c/coreboot/+/39823/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39823/1//COMMIT_MSG@14 PS1, Line 14: SOC_INTEL_TIGERLAKE_BASE SOC_INTEL_TIGERLAKE_BASE_COPY ?
One could also use SOC_INTEL_JASPERLAKE_BASE
https://review.coreboot.org/c/coreboot/+/39823/1//COMMIT_MSG@16 PS1, Line 16: tgl TGL
https://review.coreboot.org/c/coreboot/+/39823/1//COMMIT_MSG@16 PS1, Line 16: jsl JSL
https://review.coreboot.org/c/coreboot/+/39823/1//COMMIT_MSG@18 PS1, Line 18: directive plural: directives
https://review.coreboot.org/c/coreboot/+/39823/1//COMMIT_MSG@18 PS1, Line 18: compile time add a hyphen: compile-time
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Rizwan Qureshi, Justin TerAvest, Angel Pons, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39823
to look at the new patch set (#2).
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
soc/intel/jasperlake: Add Jasper Lake SoC support
This is a copy patch from Tiger Lake SoC code.
The only changes done on top of copy is changing below configs: 1. SOC_INTEL_TIGERLAKE -> SOC_INTEL_TIGERLAKE_COPY 2. SOC_INTEL_JASPERLAKE -> SOC_INTEL_JASPERLAKE_COPY 3. SOC_INTEL_TIGERLAKE_BASE -> SOC_INTEL_TIGERLAKE_BASE_COPY
We started with initial assumption that JSL and TGL can co-exist. But now we see the SoC code in Tiger Lake is relying on too many compile-time directives to make two SoCs co-exist.
The split of JSL and TGL SoC code is planned as below:
1. Copy Tiger Lake SoC code as is, and change SoC Kconfig to avoid conflicts with current mainboard builds.
2. Clean up TGL code out of copy patch done in step 1. Make it JSL only code. The SoC config still kept as SOC_INTEL_JASPERLAKE_COPY.
3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can bind to SoC code from soc/intel/jasperlake. This step establishes Jasper Lake as a separate SoC.
4. Clean up current JSL code from TGL code. This step establishes Tiger Lake as a separate SoC.
BUG=b:150217037
Change-Id: I9c33f478a2f8ed5e2d8e7815821d13044d35d388 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- A src/soc/intel/jasperlake/Kconfig A src/soc/intel/jasperlake/Makefile.inc A src/soc/intel/jasperlake/acpi.c A src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl A src/soc/intel/jasperlake/acpi/gpio.asl A src/soc/intel/jasperlake/acpi/gpio_op.asl A src/soc/intel/jasperlake/acpi/ipu.asl A src/soc/intel/jasperlake/acpi/ish.asl A src/soc/intel/jasperlake/acpi/pch_glan.asl A src/soc/intel/jasperlake/acpi/pch_hda.asl A src/soc/intel/jasperlake/acpi/pci_irqs.asl A src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl A src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl A src/soc/intel/jasperlake/acpi/pcie.asl A src/soc/intel/jasperlake/acpi/platform.asl A src/soc/intel/jasperlake/acpi/pmc.asl A src/soc/intel/jasperlake/acpi/scs.asl A src/soc/intel/jasperlake/acpi/serialio.asl A src/soc/intel/jasperlake/acpi/smbus.asl A src/soc/intel/jasperlake/acpi/southbridge.asl A src/soc/intel/jasperlake/acpi/xhci.asl A src/soc/intel/jasperlake/acpi/xhci_jsl.asl A src/soc/intel/jasperlake/acpi/xhci_tgl.asl A src/soc/intel/jasperlake/bootblock/bootblock.c A src/soc/intel/jasperlake/bootblock/cpu.c A src/soc/intel/jasperlake/bootblock/pch.c A src/soc/intel/jasperlake/bootblock/report_platform.c A src/soc/intel/jasperlake/chip.c A src/soc/intel/jasperlake/chip.h A src/soc/intel/jasperlake/cpu.c A src/soc/intel/jasperlake/elog.c A src/soc/intel/jasperlake/espi.c A src/soc/intel/jasperlake/finalize.c A src/soc/intel/jasperlake/fsp_params_jsl.c A src/soc/intel/jasperlake/fsp_params_tgl.c A src/soc/intel/jasperlake/gpio_jsl.c A src/soc/intel/jasperlake/gpio_tgl.c A src/soc/intel/jasperlake/graphics.c A src/soc/intel/jasperlake/gspi.c A src/soc/intel/jasperlake/i2c.c A src/soc/intel/jasperlake/include/soc/bootblock.h A src/soc/intel/jasperlake/include/soc/cpu.h A src/soc/intel/jasperlake/include/soc/espi.h A src/soc/intel/jasperlake/include/soc/gpe.h A src/soc/intel/jasperlake/include/soc/gpio.h A src/soc/intel/jasperlake/include/soc/gpio_defs.h A src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h A src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h A src/soc/intel/jasperlake/include/soc/iomap.h A src/soc/intel/jasperlake/include/soc/irq.h A src/soc/intel/jasperlake/include/soc/irq_jsl.h A src/soc/intel/jasperlake/include/soc/irq_tgl.h A src/soc/intel/jasperlake/include/soc/itss.h A src/soc/intel/jasperlake/include/soc/me.h A src/soc/intel/jasperlake/include/soc/meminit_jsl.h A src/soc/intel/jasperlake/include/soc/meminit_tgl.h A src/soc/intel/jasperlake/include/soc/msr.h A src/soc/intel/jasperlake/include/soc/nvs.h A src/soc/intel/jasperlake/include/soc/p2sb.h A src/soc/intel/jasperlake/include/soc/pch.h A src/soc/intel/jasperlake/include/soc/pci_devs.h A src/soc/intel/jasperlake/include/soc/pcr_ids.h A src/soc/intel/jasperlake/include/soc/pm.h A src/soc/intel/jasperlake/include/soc/pmc.h A src/soc/intel/jasperlake/include/soc/ramstage.h A src/soc/intel/jasperlake/include/soc/romstage.h A src/soc/intel/jasperlake/include/soc/serialio.h A src/soc/intel/jasperlake/include/soc/smbus.h A src/soc/intel/jasperlake/include/soc/soc_chip.h A src/soc/intel/jasperlake/include/soc/systemagent.h A src/soc/intel/jasperlake/include/soc/usb.h A src/soc/intel/jasperlake/lockdown.c A src/soc/intel/jasperlake/meminit_jsl.c A src/soc/intel/jasperlake/meminit_tgl.c A src/soc/intel/jasperlake/p2sb.c A src/soc/intel/jasperlake/pmc.c A src/soc/intel/jasperlake/pmutil.c A src/soc/intel/jasperlake/reset.c A src/soc/intel/jasperlake/romstage/Makefile.inc A src/soc/intel/jasperlake/romstage/fsp_params_jsl.c A src/soc/intel/jasperlake/romstage/fsp_params_tgl.c A src/soc/intel/jasperlake/romstage/pch.c A src/soc/intel/jasperlake/romstage/romstage.c A src/soc/intel/jasperlake/romstage/systemagent.c A src/soc/intel/jasperlake/sd.c A src/soc/intel/jasperlake/smihandler.c A src/soc/intel/jasperlake/smmrelocate.c A src/soc/intel/jasperlake/spi.c A src/soc/intel/jasperlake/systemagent.c A src/soc/intel/jasperlake/uart.c 93 files changed, 10,462 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/39823/2
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/c/coreboot/+/39823/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39823/1//COMMIT_MSG@14 PS1, Line 14: SOC_INTEL_TIGERLAKE_BASE
SOC_INTEL_TIGERLAKE_BASE_COPY ? […]
Yes, had to be SOC_INTEL_TIGERLAKE_BASE_COPY. updated.
https://review.coreboot.org/c/coreboot/+/39823/1//COMMIT_MSG@16 PS1, Line 16: jsl
JSL
Done
https://review.coreboot.org/c/coreboot/+/39823/1//COMMIT_MSG@16 PS1, Line 16: tgl
TGL
Done
https://review.coreboot.org/c/coreboot/+/39823/1//COMMIT_MSG@18 PS1, Line 18: compile time
add a hyphen: compile-time
Done
https://review.coreboot.org/c/coreboot/+/39823/1//COMMIT_MSG@18 PS1, Line 18: directive
plural: directives
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/39823/2/src/soc/intel/jasperlake/ac... File src/soc/intel/jasperlake/acpi/pci_irqs.asl:
https://review.coreboot.org/c/coreboot/+/39823/2/src/soc/intel/jasperlake/ac... PS2, Line 16: SOC_INTEL_TIGERLAKE_COPY Was this required? I believe keeping SOC_INTEL_TIGERLAKE here would have been just fine? No board should be including the asl file from jasperlake yet.
I am guessing you did a find/replace for all occurrences of SOC_INTEL_TIGERLAKE and other Kconfigs. Humm.. That should work okay.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG@23 PS2, Line 23: to avoid conflicts with current mainboard builds. Please argue why everything has to be split, and why no common code between the two can exist?
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG@22 PS2, Line 22: 1. Copy Tiger Lake SoC code as is, and change SoC Kconfig : to avoid conflicts with current mainboard builds. : : 2. Clean up TGL code out of copy patch done in step 1. : Make it JSL only code. The SoC config still kept as : SOC_INTEL_JASPERLAKE_COPY. : : 3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to : SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can : bind to SoC code from soc/intel/jasperlake. This step establishes : Jasper Lake as a separate SoC. : : 4. Clean up current JSL code from TGL code. This step establishes Tiger : Lake as a separate SoC. Please re-flow for 72/75 characters per line.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Rizwan Qureshi, Justin TerAvest, Angel Pons, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39823
to look at the new patch set (#3).
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
soc/intel/jasperlake: Add Jasper Lake SoC support
This is a copy patch from Tiger Lake SoC code.
The only changes done on top of copy is changing below configs: 1. SOC_INTEL_TIGERLAKE -> SOC_INTEL_TIGERLAKE_COPY 2. SOC_INTEL_JASPERLAKE -> SOC_INTEL_JASPERLAKE_COPY 3. SOC_INTEL_TIGERLAKE_BASE -> SOC_INTEL_TIGERLAKE_BASE_COPY
We started with initial assumption that JSL and TGL can co-exist. But now we see the SoC code in Tiger Lake is relying on too many compile-time directives to make two SoCs co-exist.
The split of JSL and TGL SoC code is planned as below:
1. Copy Tiger Lake SoC code as is, and change SoC Kconfig to avoid conflicts with current mainboard builds.
2. Clean up TGL code out of copy patch done in step 1. Make it JSL only code. The SoC config still kept as SOC_INTEL_JASPERLAKE_COPY.
3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can bind to SoC code from soc/intel/jasperlake. This step establishes Jasper Lake as a separate SoC.
4. Clean up current JSL code from TGL code. This step establishes Tiger Lake as a separate SoC.
BUG=b:150217037
Change-Id: I9c33f478a2f8ed5e2d8e7815821d13044d35d388 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- A src/soc/intel/jasperlake/Kconfig A src/soc/intel/jasperlake/Makefile.inc A src/soc/intel/jasperlake/acpi.c A src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl A src/soc/intel/jasperlake/acpi/gpio.asl A src/soc/intel/jasperlake/acpi/gpio_op.asl A src/soc/intel/jasperlake/acpi/ipu.asl A src/soc/intel/jasperlake/acpi/ish.asl A src/soc/intel/jasperlake/acpi/pch_glan.asl A src/soc/intel/jasperlake/acpi/pch_hda.asl A src/soc/intel/jasperlake/acpi/pci_irqs.asl A src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl A src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl A src/soc/intel/jasperlake/acpi/pcie.asl A src/soc/intel/jasperlake/acpi/platform.asl A src/soc/intel/jasperlake/acpi/pmc.asl A src/soc/intel/jasperlake/acpi/scs.asl A src/soc/intel/jasperlake/acpi/serialio.asl A src/soc/intel/jasperlake/acpi/smbus.asl A src/soc/intel/jasperlake/acpi/southbridge.asl A src/soc/intel/jasperlake/acpi/xhci.asl A src/soc/intel/jasperlake/acpi/xhci_jsl.asl A src/soc/intel/jasperlake/acpi/xhci_tgl.asl A src/soc/intel/jasperlake/bootblock/bootblock.c A src/soc/intel/jasperlake/bootblock/cpu.c A src/soc/intel/jasperlake/bootblock/pch.c A src/soc/intel/jasperlake/bootblock/report_platform.c A src/soc/intel/jasperlake/chip.c A src/soc/intel/jasperlake/chip.h A src/soc/intel/jasperlake/cpu.c A src/soc/intel/jasperlake/elog.c A src/soc/intel/jasperlake/espi.c A src/soc/intel/jasperlake/finalize.c A src/soc/intel/jasperlake/fsp_params_jsl.c A src/soc/intel/jasperlake/fsp_params_tgl.c A src/soc/intel/jasperlake/gpio_jsl.c A src/soc/intel/jasperlake/gpio_tgl.c A src/soc/intel/jasperlake/graphics.c A src/soc/intel/jasperlake/gspi.c A src/soc/intel/jasperlake/i2c.c A src/soc/intel/jasperlake/include/soc/bootblock.h A src/soc/intel/jasperlake/include/soc/cpu.h A src/soc/intel/jasperlake/include/soc/espi.h A src/soc/intel/jasperlake/include/soc/gpe.h A src/soc/intel/jasperlake/include/soc/gpio.h A src/soc/intel/jasperlake/include/soc/gpio_defs.h A src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h A src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h A src/soc/intel/jasperlake/include/soc/iomap.h A src/soc/intel/jasperlake/include/soc/irq.h A src/soc/intel/jasperlake/include/soc/irq_jsl.h A src/soc/intel/jasperlake/include/soc/irq_tgl.h A src/soc/intel/jasperlake/include/soc/itss.h A src/soc/intel/jasperlake/include/soc/me.h A src/soc/intel/jasperlake/include/soc/meminit_jsl.h A src/soc/intel/jasperlake/include/soc/meminit_tgl.h A src/soc/intel/jasperlake/include/soc/msr.h A src/soc/intel/jasperlake/include/soc/nvs.h A src/soc/intel/jasperlake/include/soc/p2sb.h A src/soc/intel/jasperlake/include/soc/pch.h A src/soc/intel/jasperlake/include/soc/pci_devs.h A src/soc/intel/jasperlake/include/soc/pcr_ids.h A src/soc/intel/jasperlake/include/soc/pm.h A src/soc/intel/jasperlake/include/soc/pmc.h A src/soc/intel/jasperlake/include/soc/ramstage.h A src/soc/intel/jasperlake/include/soc/romstage.h A src/soc/intel/jasperlake/include/soc/serialio.h A src/soc/intel/jasperlake/include/soc/smbus.h A src/soc/intel/jasperlake/include/soc/soc_chip.h A src/soc/intel/jasperlake/include/soc/systemagent.h A src/soc/intel/jasperlake/include/soc/usb.h A src/soc/intel/jasperlake/lockdown.c A src/soc/intel/jasperlake/meminit_jsl.c A src/soc/intel/jasperlake/meminit_tgl.c A src/soc/intel/jasperlake/p2sb.c A src/soc/intel/jasperlake/pmc.c A src/soc/intel/jasperlake/pmutil.c A src/soc/intel/jasperlake/reset.c A src/soc/intel/jasperlake/romstage/Makefile.inc A src/soc/intel/jasperlake/romstage/fsp_params_jsl.c A src/soc/intel/jasperlake/romstage/fsp_params_tgl.c A src/soc/intel/jasperlake/romstage/pch.c A src/soc/intel/jasperlake/romstage/romstage.c A src/soc/intel/jasperlake/romstage/systemagent.c A src/soc/intel/jasperlake/sd.c A src/soc/intel/jasperlake/smihandler.c A src/soc/intel/jasperlake/smmrelocate.c A src/soc/intel/jasperlake/spi.c A src/soc/intel/jasperlake/systemagent.c A src/soc/intel/jasperlake/uart.c 93 files changed, 10,462 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/39823/3
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG@23 PS2, Line 23: to avoid conflicts with current mainboard builds.
Please argue why everything has to be split, and why no common code between the two can exist?
Kconfig: Multiple Kconfig options using if SOC_INTEL_{TIGERLAKE/JASPERLAKE}
GPIO: GPIO communities have their own differences. This requires conditional checks in gpio.asl, gpio.c, gpio*.h, pmc.h and gpio.asl
PCI IRQs: Set up differently for JSL and TGL
PCIe: Number of Root ports differ.
eMMC/SD: Only supported on JSL.
XHCI Different for JSL and TGL.
Memory configuration are different for JSL and TGL
FSP params for JSL, FSP params for TGL are different.
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG@22 PS2, Line 22: 1. Copy Tiger Lake SoC code as is, and change SoC Kconfig : to avoid conflicts with current mainboard builds. : : 2. Clean up TGL code out of copy patch done in step 1. : Make it JSL only code. The SoC config still kept as : SOC_INTEL_JASPERLAKE_COPY. : : 3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to : SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can : bind to SoC code from soc/intel/jasperlake. This step establishes : Jasper Lake as a separate SoC. : : 4. Clean up current JSL code from TGL code. This step establishes Tiger : Lake as a separate SoC.
Please re-flow for 72/75 characters per line.
Done
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39823/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39823/1//COMMIT_MSG@14 PS1, Line 14: SOC_INTEL_TIGERLAKE_BASE
Yes, had to be SOC_INTEL_TIGERLAKE_BASE_COPY. updated.
Done
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39823/2/src/soc/intel/jasperlake/ac... File src/soc/intel/jasperlake/acpi/pci_irqs.asl:
https://review.coreboot.org/c/coreboot/+/39823/2/src/soc/intel/jasperlake/ac... PS2, Line 16: SOC_INTEL_TIGERLAKE_COPY
Was this required? I believe keeping SOC_INTEL_TIGERLAKE here would have been just fine? No board sh […]
Done
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG@23 PS2, Line 23: to avoid conflicts with current mainboard builds.
Kconfig: Multiple Kconfig options using if SOC_INTEL_{TIGERLAKE/JASPERLAKE} […]
Ack
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG@23 PS2, Line 23: to avoid conflicts with current mainboard builds.
Ack
Thanks. Please add that to the commit message.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Rizwan Qureshi, Justin TerAvest, Angel Pons, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39823
to look at the new patch set (#4).
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
soc/intel/jasperlake: Add Jasper Lake SoC support
This is a copy patch from Tiger Lake SoC code.
The only changes done on top of copy is changing below configs: 1. SOC_INTEL_TIGERLAKE -> SOC_INTEL_TIGERLAKE_COPY 2. SOC_INTEL_JASPERLAKE -> SOC_INTEL_JASPERLAKE_COPY 3. SOC_INTEL_TIGERLAKE_BASE -> SOC_INTEL_TIGERLAKE_BASE_COPY
We started with initial assumption that JSL and TGL can co-exist. But now we see the SoC code in Tiger Lake is relying on too many compile-time directives to make two SoCs co-exist. Some of the differences are listed below:
-> Kconfig: Multiple Kconfig options using if SOC_INTEL_{TIGERLAKE/JASPERLAKE}
-> GPIO: GPIO communities have their own differences. This requires conditional checks in gpio.asl, gpio.c, gpio*.h, pmc.h and gpio.asl
-> PCI IRQs: Set up differently for JSL and TGL
-> PCIe: Number of Root ports differ.
-> eMMC/SD: Only supported on JSL.
-> USB: Number of USB port are different for JSL and TGL.
-> Memory configuration parameters are different for JSL and TGL.
-> FSP parameters for JSL and TGL are different.
The split of JSL and TGL SoC code is planned as below:
1. Copy Tiger Lake SoC code as is, and change SoC Kconfig to avoid conflicts with current mainboard builds.
2. Clean up TGL code out of copy patch done in step 1. Make it JSL only code. The SoC config still kept as SOC_INTEL_JASPERLAKE_COPY.
3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can bind to SoC code from soc/intel/jasperlake. This step establishes Jasper Lake as a separate SoC.
4. Clean up current JSL code from TGL code. This step establishes Tiger Lake as a separate SoC.
BUG=b:150217037
Change-Id: I9c33f478a2f8ed5e2d8e7815821d13044d35d388 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- A src/soc/intel/jasperlake/Kconfig A src/soc/intel/jasperlake/Makefile.inc A src/soc/intel/jasperlake/acpi.c A src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl A src/soc/intel/jasperlake/acpi/gpio.asl A src/soc/intel/jasperlake/acpi/gpio_op.asl A src/soc/intel/jasperlake/acpi/ipu.asl A src/soc/intel/jasperlake/acpi/ish.asl A src/soc/intel/jasperlake/acpi/pch_glan.asl A src/soc/intel/jasperlake/acpi/pch_hda.asl A src/soc/intel/jasperlake/acpi/pci_irqs.asl A src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl A src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl A src/soc/intel/jasperlake/acpi/pcie.asl A src/soc/intel/jasperlake/acpi/platform.asl A src/soc/intel/jasperlake/acpi/pmc.asl A src/soc/intel/jasperlake/acpi/scs.asl A src/soc/intel/jasperlake/acpi/serialio.asl A src/soc/intel/jasperlake/acpi/smbus.asl A src/soc/intel/jasperlake/acpi/southbridge.asl A src/soc/intel/jasperlake/acpi/xhci.asl A src/soc/intel/jasperlake/acpi/xhci_jsl.asl A src/soc/intel/jasperlake/acpi/xhci_tgl.asl A src/soc/intel/jasperlake/bootblock/bootblock.c A src/soc/intel/jasperlake/bootblock/cpu.c A src/soc/intel/jasperlake/bootblock/pch.c A src/soc/intel/jasperlake/bootblock/report_platform.c A src/soc/intel/jasperlake/chip.c A src/soc/intel/jasperlake/chip.h A src/soc/intel/jasperlake/cpu.c A src/soc/intel/jasperlake/elog.c A src/soc/intel/jasperlake/espi.c A src/soc/intel/jasperlake/finalize.c A src/soc/intel/jasperlake/fsp_params_jsl.c A src/soc/intel/jasperlake/fsp_params_tgl.c A src/soc/intel/jasperlake/gpio_jsl.c A src/soc/intel/jasperlake/gpio_tgl.c A src/soc/intel/jasperlake/graphics.c A src/soc/intel/jasperlake/gspi.c A src/soc/intel/jasperlake/i2c.c A src/soc/intel/jasperlake/include/soc/bootblock.h A src/soc/intel/jasperlake/include/soc/cpu.h A src/soc/intel/jasperlake/include/soc/espi.h A src/soc/intel/jasperlake/include/soc/gpe.h A src/soc/intel/jasperlake/include/soc/gpio.h A src/soc/intel/jasperlake/include/soc/gpio_defs.h A src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h A src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h A src/soc/intel/jasperlake/include/soc/iomap.h A src/soc/intel/jasperlake/include/soc/irq.h A src/soc/intel/jasperlake/include/soc/irq_jsl.h A src/soc/intel/jasperlake/include/soc/irq_tgl.h A src/soc/intel/jasperlake/include/soc/itss.h A src/soc/intel/jasperlake/include/soc/me.h A src/soc/intel/jasperlake/include/soc/meminit_jsl.h A src/soc/intel/jasperlake/include/soc/meminit_tgl.h A src/soc/intel/jasperlake/include/soc/msr.h A src/soc/intel/jasperlake/include/soc/nvs.h A src/soc/intel/jasperlake/include/soc/p2sb.h A src/soc/intel/jasperlake/include/soc/pch.h A src/soc/intel/jasperlake/include/soc/pci_devs.h A src/soc/intel/jasperlake/include/soc/pcr_ids.h A src/soc/intel/jasperlake/include/soc/pm.h A src/soc/intel/jasperlake/include/soc/pmc.h A src/soc/intel/jasperlake/include/soc/ramstage.h A src/soc/intel/jasperlake/include/soc/romstage.h A src/soc/intel/jasperlake/include/soc/serialio.h A src/soc/intel/jasperlake/include/soc/smbus.h A src/soc/intel/jasperlake/include/soc/soc_chip.h A src/soc/intel/jasperlake/include/soc/systemagent.h A src/soc/intel/jasperlake/include/soc/usb.h A src/soc/intel/jasperlake/lockdown.c A src/soc/intel/jasperlake/meminit_jsl.c A src/soc/intel/jasperlake/meminit_tgl.c A src/soc/intel/jasperlake/p2sb.c A src/soc/intel/jasperlake/pmc.c A src/soc/intel/jasperlake/pmutil.c A src/soc/intel/jasperlake/reset.c A src/soc/intel/jasperlake/romstage/Makefile.inc A src/soc/intel/jasperlake/romstage/fsp_params_jsl.c A src/soc/intel/jasperlake/romstage/fsp_params_tgl.c A src/soc/intel/jasperlake/romstage/pch.c A src/soc/intel/jasperlake/romstage/romstage.c A src/soc/intel/jasperlake/romstage/systemagent.c A src/soc/intel/jasperlake/sd.c A src/soc/intel/jasperlake/smihandler.c A src/soc/intel/jasperlake/smmrelocate.c A src/soc/intel/jasperlake/spi.c A src/soc/intel/jasperlake/systemagent.c A src/soc/intel/jasperlake/uart.c 93 files changed, 10,462 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/39823/4
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39823/2//COMMIT_MSG@23 PS2, Line 23: to avoid conflicts with current mainboard builds.
Thanks. Please add that to the commit message.
Done
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 4: Code-Review+2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39823/5/src/soc/intel/jasperlake/in... File src/soc/intel/jasperlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/39823/5/src/soc/intel/jasperlake/in... PS5, Line 20: void mainboard_memory_init_params(FSPM_UPD *mupd); need consistent spacing around '*' (ctx:WxV)
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39823/5/src/soc/intel/jasperlake/in... File src/soc/intel/jasperlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/39823/5/src/soc/intel/jasperlake/in... PS5, Line 20: void mainboard_memory_init_params(FSPM_UPD *mupd);
need consistent spacing around '*' (ctx:WxV)
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
Patch Set 5: Code-Review+1
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39823 )
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
soc/intel/jasperlake: Add Jasper Lake SoC support
This is a copy patch from Tiger Lake SoC code.
The only changes done on top of copy is changing below configs: 1. SOC_INTEL_TIGERLAKE -> SOC_INTEL_TIGERLAKE_COPY 2. SOC_INTEL_JASPERLAKE -> SOC_INTEL_JASPERLAKE_COPY 3. SOC_INTEL_TIGERLAKE_BASE -> SOC_INTEL_TIGERLAKE_BASE_COPY
We started with initial assumption that JSL and TGL can co-exist. But now we see the SoC code in Tiger Lake is relying on too many compile-time directives to make two SoCs co-exist. Some of the differences are listed below:
-> Kconfig: Multiple Kconfig options using if SOC_INTEL_{TIGERLAKE/JASPERLAKE}
-> GPIO: GPIO communities have their own differences. This requires conditional checks in gpio.asl, gpio.c, gpio*.h, pmc.h and gpio.asl
-> PCI IRQs: Set up differently for JSL and TGL
-> PCIe: Number of Root ports differ.
-> eMMC/SD: Only supported on JSL.
-> USB: Number of USB port are different for JSL and TGL.
-> Memory configuration parameters are different for JSL and TGL.
-> FSP parameters for JSL and TGL are different.
The split of JSL and TGL SoC code is planned as below:
1. Copy Tiger Lake SoC code as is, and change SoC Kconfig to avoid conflicts with current mainboard builds.
2. Clean up TGL code out of copy patch done in step 1. Make it JSL only code. The SoC config still kept as SOC_INTEL_JASPERLAKE_COPY.
3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can bind to SoC code from soc/intel/jasperlake. This step establishes Jasper Lake as a separate SoC.
4. Clean up current JSL code from TGL code. This step establishes Tiger Lake as a separate SoC.
BUG=b:150217037
Change-Id: I9c33f478a2f8ed5e2d8e7815821d13044d35d388 Signed-off-by: Aamir Bohra aamir.bohra@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39823 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Karthik Ramasubramanian kramasub@google.com --- A src/soc/intel/jasperlake/Kconfig A src/soc/intel/jasperlake/Makefile.inc A src/soc/intel/jasperlake/acpi.c A src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl A src/soc/intel/jasperlake/acpi/gpio.asl A src/soc/intel/jasperlake/acpi/gpio_op.asl A src/soc/intel/jasperlake/acpi/ipu.asl A src/soc/intel/jasperlake/acpi/ish.asl A src/soc/intel/jasperlake/acpi/pch_glan.asl A src/soc/intel/jasperlake/acpi/pch_hda.asl A src/soc/intel/jasperlake/acpi/pci_irqs.asl A src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl A src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl A src/soc/intel/jasperlake/acpi/pcie.asl A src/soc/intel/jasperlake/acpi/platform.asl A src/soc/intel/jasperlake/acpi/pmc.asl A src/soc/intel/jasperlake/acpi/scs.asl A src/soc/intel/jasperlake/acpi/serialio.asl A src/soc/intel/jasperlake/acpi/smbus.asl A src/soc/intel/jasperlake/acpi/southbridge.asl A src/soc/intel/jasperlake/acpi/xhci.asl A src/soc/intel/jasperlake/acpi/xhci_jsl.asl A src/soc/intel/jasperlake/acpi/xhci_tgl.asl A src/soc/intel/jasperlake/bootblock/bootblock.c A src/soc/intel/jasperlake/bootblock/cpu.c A src/soc/intel/jasperlake/bootblock/pch.c A src/soc/intel/jasperlake/bootblock/report_platform.c A src/soc/intel/jasperlake/chip.c A src/soc/intel/jasperlake/chip.h A src/soc/intel/jasperlake/cpu.c A src/soc/intel/jasperlake/elog.c A src/soc/intel/jasperlake/espi.c A src/soc/intel/jasperlake/finalize.c A src/soc/intel/jasperlake/fsp_params_jsl.c A src/soc/intel/jasperlake/fsp_params_tgl.c A src/soc/intel/jasperlake/gpio_jsl.c A src/soc/intel/jasperlake/gpio_tgl.c A src/soc/intel/jasperlake/graphics.c A src/soc/intel/jasperlake/gspi.c A src/soc/intel/jasperlake/i2c.c A src/soc/intel/jasperlake/include/soc/bootblock.h A src/soc/intel/jasperlake/include/soc/cpu.h A src/soc/intel/jasperlake/include/soc/espi.h A src/soc/intel/jasperlake/include/soc/gpe.h A src/soc/intel/jasperlake/include/soc/gpio.h A src/soc/intel/jasperlake/include/soc/gpio_defs.h A src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h A src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h A src/soc/intel/jasperlake/include/soc/iomap.h A src/soc/intel/jasperlake/include/soc/irq.h A src/soc/intel/jasperlake/include/soc/irq_jsl.h A src/soc/intel/jasperlake/include/soc/irq_tgl.h A src/soc/intel/jasperlake/include/soc/itss.h A src/soc/intel/jasperlake/include/soc/me.h A src/soc/intel/jasperlake/include/soc/meminit_jsl.h A src/soc/intel/jasperlake/include/soc/meminit_tgl.h A src/soc/intel/jasperlake/include/soc/msr.h A src/soc/intel/jasperlake/include/soc/nvs.h A src/soc/intel/jasperlake/include/soc/p2sb.h A src/soc/intel/jasperlake/include/soc/pch.h A src/soc/intel/jasperlake/include/soc/pci_devs.h A src/soc/intel/jasperlake/include/soc/pcr_ids.h A src/soc/intel/jasperlake/include/soc/pm.h A src/soc/intel/jasperlake/include/soc/pmc.h A src/soc/intel/jasperlake/include/soc/ramstage.h A src/soc/intel/jasperlake/include/soc/romstage.h A src/soc/intel/jasperlake/include/soc/serialio.h A src/soc/intel/jasperlake/include/soc/smbus.h A src/soc/intel/jasperlake/include/soc/soc_chip.h A src/soc/intel/jasperlake/include/soc/systemagent.h A src/soc/intel/jasperlake/include/soc/usb.h A src/soc/intel/jasperlake/lockdown.c A src/soc/intel/jasperlake/meminit_jsl.c A src/soc/intel/jasperlake/meminit_tgl.c A src/soc/intel/jasperlake/p2sb.c A src/soc/intel/jasperlake/pmc.c A src/soc/intel/jasperlake/pmutil.c A src/soc/intel/jasperlake/reset.c A src/soc/intel/jasperlake/romstage/Makefile.inc A src/soc/intel/jasperlake/romstage/fsp_params_jsl.c A src/soc/intel/jasperlake/romstage/fsp_params_tgl.c A src/soc/intel/jasperlake/romstage/pch.c A src/soc/intel/jasperlake/romstage/romstage.c A src/soc/intel/jasperlake/romstage/systemagent.c A src/soc/intel/jasperlake/sd.c A src/soc/intel/jasperlake/smihandler.c A src/soc/intel/jasperlake/smmrelocate.c A src/soc/intel/jasperlake/spi.c A src/soc/intel/jasperlake/systemagent.c A src/soc/intel/jasperlake/uart.c 93 files changed, 10,462 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved Subrata Banik: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved
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Aamir Bohra (Code Review) -
Angel Pons (Code Review)
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build bot (Jenkins) (Code Review)
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Furquan Shaikh (Code Review)
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Karthik Ramasubramanian (Code Review)
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Paul Menzel (Code Review)
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Subrata Banik (Code Review)