Attention is currently required from: Rizwan Qureshi, Subrata Banik, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55653 )
Change subject: soc/intel/common/../car: Add CAR debug Kconfig CAR_DEBUG ......................................................................
Patch Set 1: Code-Review-2
(4 comments)
File src/soc/intel/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/55653/comment/ca57d9b0_4416c450 PS1, Line 82: CAR_DEBUG This is not used in this CL?
File src/soc/intel/common/block/cpu/cpulib.c:
https://review.coreboot.org/c/coreboot/+/55653/comment/42012cc4_b4404a77 PS1, Line 459: res = cpuid_ext(0x04, 0x03); : : const size_t assoc = CPUID_CACHE_WAYS_OF_ASSOC(res) + 1; : const size_t partitions = CPUID_CACHE_PHYS_LINE(res) + 1; : const size_t cache_line_size = CPUID_CACHE_COHER_LINE(res) + 1; : const size_t number_of_sets = CPUID_CACHE_NO_OF_SETS(res) + 1; : const size_t cache_size = assoc * partitions * cache_line_size * number_of_sets; : printk(BIOS_INFO, "assoc=%zd par=%zd line_size=%zd sets=%zd\n", : assoc, partitions, cache_line_size, number_of_sets); : printk(BIOS_INFO, "@@ cache_size 0x%lx bytes\n", cache_size); Is this Intel specific? If not, can it be moved to cpu/x86?
https://review.coreboot.org/c/coreboot/+/55653/comment/a4b29865_a9af9bec PS1, Line 470: addr < 0xFFFF0000 Why from 0xFF000000 to 0xFFFF0000? What is special about that? It looks like you are trying to avoid the bootblock. Do you expect to memcpy data from the flash to CAR? Then you should assert that you are in fact in ENV_CACHE_AS_RAM. Open coding the flash addresses like this is a bad idea.
https://review.coreboot.org/c/coreboot/+/55653/comment/51a37e06_3fba888a PS1, Line 472: BIOS_ERR Those are not errors
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Arthur Heymans (Code Review)